|COMP||1||—||Device compensation input. A resistor and capacitor
from this pin to GOSNS define the compensation of the control loop.
In stacked operation, connect the COMP pins of all stacked devices together and connect a resistor and capacitor between the common COMP node and GOSNS.
|GOSNS||2||I||Output ground sense (differential output voltage sensing)|
|VOSNS||3||I||Output voltage sense (differential output voltage sensing)|
|EN||4||I||This is the enable pin of the device. The user must
connect to this pin using a series resistor of at least 15 kΩ. A low
logic level on this pin disables the device and a high logic level
on this pin enables the device. Do not leave this pin
For stacked operation, interconnect EN pins of all stacked devices with a resistor to the supply voltage or a GPIO of a processor. See Section 9.3.17 for a detailed description.
|VIN||5, 9||P||Power supply input. Connect the input capacitor as close as possible between VIN and GND.|
|GND||6, 8||GND||Ground pin|
|SW||7||O||This pin is the switch pin of the converter and is connected to the internal power MOSFETs.|
|PG||10||I/O||Open-drain power-good output. Low impedance when not
"power good," high impedance when "power good." This pin can be left
open or be tied to GND when not used in single device operation.
In stacked operation, interconnect the PG pins of all stacked devices. Only the PG pin of the primary converter in stacked operation is an open-drain output. For devices that are defined as secondary converters in stacked mode, this pin is an input pin. See Section 9.3.17 for a detailed description.
|MODE/SYNC||11||I||The device runs in power save mode when this pin is pulled low. If the pin is pulled high, the device runs in forced-PWM mode. Do not leave this pin unconnected. The mode pin can also be used to synchronize the device to an external clock.|
|SDA||12||I/O||I2C serial data pin. Do not leave
floating. Connect a pullup resistor to a logic high level.
Connect to GND for secondary devices in stacked operation and for device variants without I2C.
|SCL||13||I/O||I2C serial clock pin. Do not leave this
pin floating. Connect a pullup resistor to a logic high level.
Connect this pin to GND for secondary devices in stacked operation and for device variants without I2C.
|SYNC_OUT||14||O||Internal clock output pin for synchronization in
stacked mode. Leave this pin floating for single device operation.
Connect this pin to the MODE/SYNC pin of the next device in the
daisy-chain in stacked operation. Do not use this pin to connect
to a non-TPS6287x-Q1
During start-up, this pin is used to identify if a device must operate as a secondary converter in stacked operation. Connect a 47-kΩ resistor from this pin to GND to define a secondary converter in stacked operation. See Section 9.3.17 for a detailed description.
|VSEL||15||—||Start-up output voltage select pin. A resistor or short circuit to GND or VIN defines the selected output voltage. See Section 22.214.171.124.|
|FSEL||16||—||Frequency select pin. A resistor or a short circuit to GND or VIN determines the free-running switching frequency. See Section 126.96.36.199.|
|Exposed Thermal Pad||—||The thermal pad must be soldered to GND to achieve an appropriate thermal resistance and for mechanical stability.|