ZHCSQI6A May   2022  – July 2022 TPS62870-Q1 , TPS62871-Q1 , TPS62872-Q1 , TPS62873-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. 说明(续)
  6. Device Options
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 I2C Interface Timing Characteristics
    7. 8.7 Timing Requirements
    8. 8.8 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Fixed-Frequency DCS Control Topology
      2. 9.3.2  Forced PWM and Power Save Modes
      3. 9.3.3  Precise Enable
      4. 9.3.4  Start-Up
      5. 9.3.5  Switching Frequency Selection
      6. 9.3.6  Output Voltage Setting
        1. 9.3.6.1 Output Voltage Range
        2. 9.3.6.2 Output Voltage Setpoint
        3. 9.3.6.3 Non-Default Output Voltage Setpoint
        4. 9.3.6.4 Dynamic Voltage Scaling
      7. 9.3.7  Compensation (COMP)
      8. 9.3.8  Mode Selection and Clock Synchronization (MODE/SYNC)
      9. 9.3.9  Spread Spectrum Clocking (SSC)
      10. 9.3.10 Output Discharge
      11. 9.3.11 Undervoltage Lockout (UVLO)
      12. 9.3.12 Overvoltage Lockout (OVLO)
      13. 9.3.13 Overcurrent Protection
        1. 9.3.13.1 Cycle-by-Cycle Current Limiting
        2. 9.3.13.2 Hiccup Mode
        3. 9.3.13.3 Current Limit Mode
      14. 9.3.14 Power Good (PG)
        1. 9.3.14.1 Standalone or Primary Device Behavior
        2. 9.3.14.2 Secondary Device Behavior
      15. 9.3.15 Remote Sense
      16. 9.3.16 Thermal Warning and Shutdown
      17. 9.3.17 Stacked Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-On Reset
      2. 9.4.2 Undervoltage Lockout
      3. 9.4.3 Standby
      4. 9.4.4 On
    5. 9.5 Programming
      1. 9.5.1 Serial Interface Description
      2. 9.5.2 Standard, Fast, Fast Mode Plus Protocol
      3. 9.5.3 I2C Update Sequence
    6. 9.6 Register Map
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Selecting the Inductor
        2. 10.2.2.2 Selecting the Input Capacitors
        3. 10.2.2.3 Selecting the Compensation Resistor
        4. 10.2.2.4 Selecting the Output Capacitors
        5. 10.2.2.5 Selecting the Compensation Capacitor, CC
        6. 10.2.2.6 Selecting the Compensation Capacitor, CC2
      3. 10.2.3 Application Curves
    3. 10.3 Best Design Practices
    4. 10.4 Power Supply Recommendations
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

Stacked Operation

The user can connect multiple devices in parallel in what is known as a "stack"; for example, to increase output current capability or reduce device junction temperature. A stack comprises one primary device and one or more secondary devices. During initialization, each device monitors its SYNC_OUT pin to determine if should operate as a primary device or a secondary device:

  • If there is a 47-kΩ resistor between the SYNC_OUT pin and ground, the device operates as a secondary device.
  • If the SYNC_OUT pin is high impedance, the device operates as a primary device.

Figure 9-14 shows the recommended interconnections in a stack of two TPS6287x-Q1 devices.



Figure 9-14 Two TPS6287x-Q1 Devices in a Stacked Configuration

The key points to note are:

  • All the devices in the stack share a common enable signal, which must be pulled up with a resistance of at least 15 kΩ.
  • All the devices in the stack share a common power-good signal.
  • All the devices in the stack share a common compensation signal.
  • The remote sense pins (VOSNS and GOSNS) of each device must be connected (do not leave these pins floating).
  • Each device must be configured for the same switching frequency.
  • The primary device must be configured for forced PWM operation (secondary devices are automatically configured for forced PWM operation).
  • A stacked configuration can support synchronization to an external clock or spread-spectrum clocking.
  • Only the VSEL pin of the primary device is used to set the default output voltage. The VSEL pin of secondary devices is not used and should be connected to ground.
  • The SDA and SCL pins of secondary devices are not used and should be connected to ground.
  • A stacked configuration uses a daisy-chained clocking signal, in which each device switches with a phase offset of approximately 140° relative to the adjacent devices in the daisy-chain. To daisy-chain the clocking signal, connect the SYNC_OUT pin of the primary device to the MODE/SYNC pin of the first secondary device. Connect the SYNC_OUT pin of the first secondary device to the MODE/SYNC pin of the second secondary device. Continue this connection scheme for all devices in the stack, to daisy-chain them together.
  • Hiccup overcurrent protection should not be used in a stacked configuration.

In a stacked configuration, the common enable signal also acts as a SYSTEM_READY signal (see Section 9.3.3). Each device in the stack can pull its EN pin low during device start-up or when a fault occurs. Thus, the stack is only enabled when all devices have completed their start-up sequence and are fault-free. A fault in any one device disables the whole stack for as long as the fault condition exists.

During start-up, the primary converter pulls the COMP pin low for as long as the enable signal (SYSTEM_READY) is low. When the enable signal goes high, the primary device actively controls the COMP pin and all converters in the stack follow the COMP voltage. During start-up, each device in the stack pulls its PG pin low while it initializes. When initialization is complete, each secondary device in the stack sets its PG pin to a high impedance and the primary device alone controls the state of the PG signal. The PG pin goes high when the stack has completed its start-up ramp and the output voltage is within specification. The secondary converters in the stack detect the rising edge of the power-good signal and switch from DCM operation to CCM operation. After the stack has successfully started up, the primary device controls the power-good signal in the normal way. In a stacked configuration, there are some faults that only affect individual devices, and other faults that affect all devices. For example, if one device enters current limit, only that device is affected. But a thermal shutdown or undervoltage lockout event in one device disables all devices through the shared enable (SYSTEM_READY) signal.

Functionality During Stacked Operation

Some device features are not available during stacked operation, or are only available in the primary converter. Table 9-8 summarizes the available functionality during stacked operation.

Table 9-8 Functionality During Stacked Operation
Function Primary Device Secondary Device Remark
UVLO Yes Yes Common enable signal
OVLO Yes Yes Common enable signal
OCP – Current Limit Yes Yes Individual
OCP – Hiccup OCP No No Do not use during stacked operation.
Thermal Shutdown Yes Yes Common enable signal
Power-Good (Window Comparator) Yes No Primary device only
I2C Interface Yes No Primary device only
DVS Through I2C No Voltage loop controlled by primary device only
SSC Through I2C No Daisy-chained from primary device to secondary devices
SYNC Yes Yes Synchronization clock applied to primary device
Precise Enable No No Only binary enable
Output Discharge Yes Yes Always enabled in secondary devices

Fault Handling During Stacked Operation

In a stacked configuration, there are some faults that only affect individual devices and other faults that affect all devices. For example, if one device enters current limit, only that device is affected. A thermal shutdown or undervoltage lockout event in one device disables all devices through the shared enable (SYSTEM_READY) signal. Table 9-9 summarizes the fault handling of the TPS6287x-Q1 devices during stacked operation.

Table 9-9 Fault Handling During Stacked Operation
Fault Condition Device Response System Response
UVLO Enable signal pulled low New soft start
OVLO
Thermal shutdown
Current limit Enable signal remains high Error amplifier clamped