8.3.20 Power-On Reset

Upon application of minimum valid power and valid GTX_CLK with device enabled (ENABLE = HIGH), the TLK2711-SP generates a power-on reset. During the power-on reset the RXD0 to RXD15, RKLSB, and RKMSB signal pins go to a high-impedance state. The RXCLK is held low. LCKREFN must be deasserted (logic high state) with active transitions on the receiver during the power-on reset period. Active transitions on receiver can be accomplished with transitions on RXP/N or by assertion of LOOPEN. For TX-only applications, LOOPEN and LCKREFN can be driven logic high together. The receiver circuit requires this to properly reset. After power-up reset period, LCKREFN can be asserted for transmit only applications. The length of the power-on reset cycle depends on the TXCLK frequency, but is less than 1 ms. See Figure 12. TI recommends that the receiver be reset immediately after power up. In some conditions, it is possible for the receiver circuit to power up in state with internal contention.

If LCKREFN cannot be deasserted high during or for the complete power-on reset period, it can be deasserted high at the end of or after the power-on reset period for minimum of 1 µs with active transitions on receiver to properly complete reset of receiver.

Figure 12. Power-On/Reset Timing Diagram