ZHCSS40I march 1994 – march 2021 TL16C550C
PRODUCTION DATA
The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is emulating a modem. The contents of this register are summarized in Table 7-3 and are described in the following bulleted list.
When any of bits 0 through 3 are set, the associated output is forced low. When any of these bits are cleared, the associated output is forced high.
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational. The modem control interrupts are also operational, but the modem control interrupt’s sources are now the lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the IER.
The ACE flow can be configured by programming bits 1 and 5 of the MCR as shown in Table 7-8.
MCR BIT 5 (AFE) | MCR BIT 1 (RTS) | ACE FLOW CONFIGURATION |
---|---|---|
1 | 1 | Auto-RTS and auto-CTS enabled (autoflow control enabled) |
1 | 0 | Auto-CTS only enabled |
0 | X | Auto-RTS and auto-CTS disabled |