ZHCSS40I march   1994  – march 2021 TL16C550C

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 说明
  4. 3 Revision History
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Recommended Operating Conditions (Low Voltage - 3.3 nominal)
    3. 5.3  Recommended Operating Conditions (Standard Voltage - 5 V nominal)
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics (Low Voltage - 3.3 V nominal)
    6. 5.6  Electrical Characteristics (Standard Voltage - 5 V nominal)
    7. 5.7  System Timing Requirements
    8. 5.8  System Switching Characteristics
    9. 5.9  Baud Generator Switching Characteristics
    10. 5.10 Receiver Switching Characteristics
    11. 5.11 Transmitter Switching Characteristics
    12. 5.12 Modem Control Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Autoflow Control (see )
    2. 7.2 Auto-RTS (see )
    3. 7.3 Auto-CTS (see )
    4. 7.4 Enabling Autoflow Control and Auto-CTS
    5. 7.5 Auto-CTS and Auto-RTS Functional Timing
    6. 7.6 Functional Block Diagram
    7. 7.7 Principles of Operation
      1. 7.7.1  Accessible Registers
      2. 7.7.2  FIFO Control Register (FCR)
      3. 7.7.3  FIFO Interrupt Mode Operation
      4. 7.7.4  FIFO Polled Mode Operation
      5. 7.7.5  Interrupt Enable Register (IER)
      6. 7.7.6  Interrupt Identification Register (IIR)
      7. 7.7.7  Line Control Register (LCR)
      8. 7.7.8  Line Status Register (LSR)
      9. 7.7.9  Modem Control Register (MCR)
      10. 7.7.10 Modem Status Register (MSR)
      11. 7.7.11 Programming Baud Generator
      12. 7.7.12 Receiver Buffet Register (RBR)
      13. 7.7.13 Scratch Register
      14. 7.7.14 Transmitter Holding Register (THR)
  9. 8 Application Information
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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5.7 System Timing Requirements

over recommended ranges of supply voltage and operating free-air temperature
ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
tcR Cycle time, read (tw7 + td8 + td9) RC 87 ns
tcW Cycle time, write (tw6 + td5 + td6) WC 87 ns
tw1 Pulse duration, clock high tXH 5 f = 16 MHz Max,

VCC = 5 V

 25 ns
tw2 Pulse duration, clock low tXL
tw5 Pulse duration, ADS low tADS 6.7 9 ns
tw6 Pulse duration, WR tWR 6 40 ns
tw7 Pulse duration, RD tRD 7 40 ns
tw8 Pulse duration, MR tMR 1 ns
tsu1 Setup time, address valid before ADS↑ tAS 6.7 8 ns
tsu2 Setup time, CS valid before ADS↑ tCS
tsu3 Setup time, data valid before WR1↑ or WR2↓ tDS 6 15 ns
tsu4 Setup time, CTS↑ before midpoint of stop bit 17 10 ns
th1 Hold time, address low after ADS↑ tAH 6.7 0 ns
th2 Hold time, CS valid after ADS↑ tCH
th3 Hold time, CS valid after WR1↑ or WR2↓ tWCS 6 10 ns
th4 Hold time, address valid after WR1↑ or WR2↓ tWA
th5 Hold time, data valid after WR1↑ or WR2↓ tDH 6 5 ns
th6 Hold time, chip select valid after RD1↑or RD2↓ tRCS 7 10 ns
th7 Hold time, address valid after RD1↑ or RD2↓ tRA 7 20 ns
td4(1) Delay time, CS valid before WR1↓ or WR2↑ tCSW 6 7 ns
td5(1) Delay time, address valid before WR1↓ or WR2↑ tAW
td6(1) Delay time, write cycle, WR1↑ or WR2↓ to ADS↓ tWC 6 40 ns
td7(1) Delay time, CS valid to RD1↓ or RD2↑ tCSR 7 7 ns
td8(1) Delay time, address valid to RD1↓ or RD2↑ tAR
td9 Delay time, read cycle, RD1↑ or RD2↓ to ADS↓ tRC 7 40 ns
td10 Delay time, RD1↓ or RD2↑ to data valid tRVD 7 CL = 75 pF 45 ns
td11 Delay time, RD1↑ or RD2↓ to floating data tHZ 7 CL = 75 pF 20 ns
(1) Only applies when ADS is low.