The FCR is a write-only register at
the same location as the IIR, which is a read-only register. The FCR enables and
clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA
signalling.
- Bit 0: This bit, when set,
enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR
bits are written to or they are not programmed. Changing this bit clears the
FIFOs.
- Bit 1: This bit, when set, clears
all bytes in the receiver FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self clearing.
- Bit 2: This bit, when set, clears
all bytes in the transmit FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self clearing.
- Bit 3: When FCR0 is set, setting
FCR3 causes RXRDY and TXRDY to change
from level 0 to level 1.
- Bits 4 and 5: These two bits are
reserved for future use.
- Bits 6 and 7: These two bits set
the trigger level for the receiver FIFO interrupt (see Table 7-4).
Table 7-4 Receiver FIFO Trigger
Level
| BIT 7 |
BIT 6 |
RECEIVER FIFO TRIGGER LEVEL (BYTES) |
| 0 |
0 |
01 |
| 0 |
1 |
04 |
| 1 |
0 |
08 |
| 1 |
1 |
14 |