ZHCSKP3J February 2019 – August 2021 TDA4VM , TDA4VM-Q1
PRODUCTION DATA
For more details about features and additional description information on the device Universal Asynchronous Receiver Transmitter, see the corresponding sections within , Section 6.3, Signal Descriptions and Section 8, Detailed Description.
Table 7-104 represents UART timing conditions.
PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|
INPUT CONDITIONS | ||||
SRI | Input slew rate | 0.5 | 5 | V/ns |
OUTPUT CONDITIONS | ||||
CL | Output load capacitance | 1 | 30 | pF |
PCB CONNECTIVITY REQUIREMENTS | ||||
td(Trace Mismatch Delay) | Propagation delay mismatch across all traces | 100 | ps |
Section 7.10.5.25.1, Section 7.10.5.25.2, and Figure 7-119 present timing requirements and switching characteristics for UART interface.