ZHCSF47E June   2016  – December 2017 TAS2560

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化原理图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  I2C Timing Requirements
    7. 7.7  I2S/LJF/RJF Timing in Master Mode
    8. 7.8  I2S/LJF/RJF Timing in Slave Mode
    9. 7.9  DSP Timing in Master Mode
    10. 7.10 DSP Timing in Slave Mode
    11. 7.11 PDM Timing
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  General I2C Operation
      2. 9.3.2  Single-Byte and Multiple-Byte Transfers
      3. 9.3.3  Single-Byte Write
      4. 9.3.4  Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 9.3.5  Single-Byte Read
      6. 9.3.6  Multiple-Byte Read
      7. 9.3.7  PLL
      8. 9.3.8  Clock Distribution
      9. 9.3.9  Clock Error Detection
      10. 9.3.10 Class-D Edge Rate Control
      11. 9.3.11 IV Sense
      12. 9.3.12 Boost Control
      13. 9.3.13 Thermal Fold-back
      14. 9.3.14 Battery Guard AGC
      15. 9.3.15 Configurable Boost Current Limit (ILIM)
      16. 9.3.16 Fault Protection
        1. 9.3.16.1 Speaker Over-Current
        2. 9.3.16.2 Analog Under-Voltage
        3. 9.3.16.3 Die Over-Temperature
        4. 9.3.16.4 Clocking Faults
        5. 9.3.16.5 Brownout
      17. 9.3.17 Spread Spectrum vs Synchronized
      18. 9.3.18 IRQs and Flags
      19. 9.3.19 CRC checksum for I2C
      20. 9.3.20 PurePath Console 3 Software TAS2560 Application
    4. 9.4 Device Functional Modes
      1. 9.4.1 Audio Digital I/O Interface
        1. 9.4.1.1 I2S Mode
        2. 9.4.1.2 DSP Mode
        3. 9.4.1.3 DSP Time Slot Mode
        4. 9.4.1.4 Right-Justified Mode (RJF)
        5. 9.4.1.5 Left-Justified Mode (LJF)
        6. 9.4.1.6 Mono PCM Mode
        7. 9.4.1.7 Stereo Application Example - TDM Mode
      2. 9.4.2 PDM MODE
    5. 9.5 Operational Modes
      1. 9.5.1 Hardware Shutdown
      2. 9.5.2 Software Shutdown
      3. 9.5.3 Low Power Sleep
      4. 9.5.4 Software Reset
      5. 9.5.5 Device Processing Modes
        1. 9.5.5.1 Mode 1 - PCM input playback only
        2. 9.5.5.2 Mode 2 - PCM input playback + PCM IVsense output
        3. 9.5.5.3 Mode 2 96k
        4. 9.5.5.4 Mode 3 - PCM input playback + PDM IVsense output
        5. 9.5.5.5 Mode 4 - PDM input playback only
        6. 9.5.5.6 Mode 5 - PDM input playback + PDM IVsense output
    6. 9.6 Programming
      1. 9.6.1 Device Power Up and Un-mute Sequence 8Ω load
      2. 9.6.2 Device Power Up and Un-mute Sequence 4Ω or 6Ω load
      3. 9.6.3 Mute and Device Power Down Sequence
    7. 9.7 Register Map
      1. 9.7.1  Register Map Summary
        1. 9.7.1.1 Register Summary Table
      2. 9.7.2  PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
        1. Table 60. Page Select Field Descriptions
      3. 9.7.3  RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
        1. Table 61. Software Reset Field Descriptions
      4. 9.7.4  MODE (book=0x00 page=0x00 address=0x02) [reset=1h]
        1. Table 62. Mode Control Field Descriptions
      5. 9.7.5  SPK_CTRL (book=0x00 page=0x00 address=0x04) [reset=5Fh]
        1. Table 63. Speaker Control Field Descriptions
      6. 9.7.6  PWR_CTRL_2 (book=0x00 page=0x00 address=0x05) [reset=0h]
        1. Table 64. Power Up Control 2 Field Descriptions
      7. 9.7.7  PWR_CTRL_1 (book=0x00 page=0x00 address=0x07) [reset=0h]
        1. Table 65. Power Up Control 1 Field Descriptions
      8. 9.7.8  RAMP_CTRL (book=0x00 page=0x00 address=0x08) [reset=1h]
        1. Table 66. Class Field Descriptions
      9. 9.7.9  EDGE_ISNS_BOOST (book=0x00 page=0x00 address=0x09) [reset=83h]
        1. Table 67. Edge Rate, Isense Scale, Boost limit Field Descriptions
      10. 9.7.10 PLL_CLKIN (book=0x00 page=0x00 address=0x0F) [reset=41h]
        1. Table 68. PLL Clock Input Control Field Descriptions
      11. 9.7.11 PLL_JVAL (book=0x00 page=0x00 address=0x10) [reset=4h]
        1. Table 69. PLL J Multiplier Control Field Descriptions
      12. 9.7.12 PLL_DVAL_1 (book=0x00 page=0x00 address=0x11) [reset=0h]
        1. Table 70. PLL Fractional Multiplier D Val MSB Field Descriptions
      13. 9.7.13 PLL_DVAL_2 (book=0x00 page=0x00 address=0x12) [reset=0h]
        1. Table 71. PLL Fractional Multiplier D Val LSB Field Descriptions
      14. 9.7.14 ASI_FORMAT (book=0x00 page=0x00 address=0x14) [reset=2h]
        1. Table 72. ASI Mode Control Field Descriptions
      15. 9.7.15 ASI_CHANNEL (book=0x00 page=0x00 address=0x15) [reset=0h]
        1. Table 73. ASI Channel Control Field Descriptions
      16. 9.7.16 ASI_OFFSET_1 (book=0x00 page=0x00 address=0x16) [reset=0h]
        1. Table 74. ASI Offset Field Descriptions
      17. 9.7.17 ASI_OFFSET_2 (book=0x00 page=0x00 address=0x17) [reset=0h]
        1. Table 75. ASI Offset Second Slot Field Descriptions
      18. 9.7.18 ASI_CFG_1 (book=0x00 page=0x00 address=0x18) [reset=0h]
        1. Table 76. ASI Configuration Field Descriptions
      19. 9.7.19 ASI_DIV_SRC (book=0x00 page=0x00 address=0x19) [reset=0h]
        1. Table 77. ASI BDIV Clock Input Field Descriptions
      20. 9.7.20 ASI_BDIV (book=0x00 page=0x00 address=0x1A) [reset=1h]
        1. Table 78. ASI BDIV Configuration Field Descriptions
      21. 9.7.21 ASI_WDIV (book=0x00 page=0x00 address=0x1B) [reset=40h]
        1. Table 79. ASI WDIV Configuration Field Descriptions
      22. 9.7.22 PDM_CFG (book=0x00 page=0x00 address=0x1C) [reset=0h]
        1. Table 80. PDM Configuration Field Descriptions
      23. 9.7.23 PDM_DIV (book=0x00 page=0x00 address=0x1D) [reset=8h]
        1. Table 81. PDM Divider Configuration Field Descriptions
      24. 9.7.24 DSD_DIV (book=0x00 page=0x00 address=0x1E) [reset=8h]
        1. Table 82. DSD Divider Configuration Field Descriptions
      25. 9.7.25 CLK_ERR_1 (book=0x00 page=0x00 address=0x21) [reset=3h]
        1. Table 83. Clock Error and DSP memory Reload Field Descriptions
      26. 9.7.26 CLK_ERR_2 (book=0x00 page=0x00 address=0x22) [reset=3Fh]
        1. Table 84. Clock Error Configuration Field Descriptions
      27. 9.7.27 IRQ_PIN_CFG (book=0x00 page=0x00 address=0x23) [reset=21h]
        1. Table 85. Interrupt Pin Configuration Field Descriptions
      28. 9.7.28 INT_CFG_1 (book=0x00 page=0x00 address=0x24) [reset=0h]
        1. Table 86. Interrupt Configuration 1 Field Descriptions
      29. 9.7.29 INT_CFG_2 (book=0x00 page=0x00 address=0x25) [reset=0h]
        1. Table 87. Interrupt Configuration 2 Field Descriptions
      30. 9.7.30 INT_DET_1 (book=0x00 page=0x00 address=0x26) [reset=0h]
        1. Table 88. Interrupt Detected 1 Field Descriptions
      31. 9.7.31 INT_DET_2 (book=0x00 page=0x00 address=0x27) [reset=0h]
        1. Table 89. Interrupt Detected 2 Field Descriptions
      32. 9.7.32 STATUS_POWER (book=0x00 page=0x00 address=0x2A) [reset=0h]
        1. Table 90. Status Block Power Field Descriptions
      33. 9.7.33 SAR_VBAT_MSB (book=0x00 page=0x00 address=0x2D) [reset=C0h]
        1. Table 91. SAR VBAT Measurement MSB Field Descriptions
      34. 9.7.34 SAR_VBAT_LSB (book=0x00 page=0x00 address=0x2E) [reset=0h]
        1. Table 92. SAR VBAT Measurement LSB Field Descriptions
      35. 9.7.35 DIE_TEMP_SENSOR (book=0x00 page=0x00 address=0x31) [reset=0h]
        1. Table 93. Die Temperature Sensor Field Descriptions
      36. 9.7.36 LOW_PWR_MODE (book=0x00 page=0x00 address=0x35) [reset=0h]
        1. Table 94. Low Power Configuration Field Descriptions
      37. 9.7.37 PCM_RATE (book=0x00 page=0x00 address=0x36) [reset=32h]
        1. Table 95. PCM Sample Rate Field Descriptions
      38. 9.7.38 CLOCK_ERR_CFG_1 (book=0x00 page=0x00 address=0x4F) [reset=0h]
        1. Table 96. Clock Error Configuration 1 Field Descriptions
      39. 9.7.39 CLOCK_ERR_CFG_2 (book=0x00 page=0x00 address=0x50) [reset=11h]
        1. Table 97. Clock Error Configuration 2 Field Descriptions
      40. 9.7.40 PROTECTION_CFG_1 (book=0x00 page=0x00 address=0x58) [reset=3h]
        1. Table 98. Class Field Descriptions
      41. 9.7.41 CRC_CHECKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
        1. Table 99. Checksum Field Descriptions
      42. 9.7.42 BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
        1. Table 100. Book Selection Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Detailed Design Procedure
          1. 10.2.1.1.1 Mono/Stereo Configuration
          2. 10.2.1.1.2 Boost Converter Passive Devices
          3. 10.2.1.1.3 EMI Passive Devices
          4. 10.2.1.1.4 Miscellaneous Passive Devices
      2. 10.2.2 Application Performance Plots
    3. 10.3 Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
    2. 11.2 Power Supply Sequencing
      1. 11.2.1 Boost Supply Details
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
    2. 13.2 社区资源
    3. 13.3 商标
    4. 13.4 静电放电警告
    5. 13.5 Glossary
  14. 14机械、封装和可订购信息
    1. 14.1 封装尺寸

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • YFF|30
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.7.1.1 Register Summary Table

Addr Register Description Section
0x00 PAGE Page Select PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
0x01 RESET Software Reset RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
0x02 MODE Mode Control MODE (book=0x00 page=0x00 address=0x02) [reset=1h]
0x04 SPK_CTRL Speaker Control SPK_CTRL (book=0x00 page=0x00 address=0x04) [reset=5Fh]
0x05 PWR_CTRL_2 Power Up Control 2 PWR_CTRL_2 (book=0x00 page=0x00 address=0x05) [reset=0h]
0x07 PWR_CTRL_1 Power Up Control 1 PWR_CTRL_1 (book=0x00 page=0x00 address=0x07) [reset=0h]
0x08 RAMP_CTRL Class RAMP_CTRL (book=0x00 page=0x00 address=0x08) [reset=1h]
0x09 EDGE_ISNS_BOOST Edge Rate, Isense Scale, Boost limit EDGE_ISNS_BOOST (book=0x00 page=0x00 address=0x09) [reset=83h]
0x0F PLL_CLKIN PLL Clock Input Control PLL_CLKIN (book=0x00 page=0x00 address=0x0F) [reset=41h]
0x10 PLL_JVAL PLL J Multiplier Control PLL_JVAL (book=0x00 page=0x00 address=0x10) [reset=4h]
0x11 PLL_DVAL_1 PLL Fractional Multiplier D Val MSB PLL_DVAL_1 (book=0x00 page=0x00 address=0x11) [reset=0h]
0x12 PLL_DVAL_2 PLL Fractional Multiplier D Val LSB PLL_DVAL_2 (book=0x00 page=0x00 address=0x12) [reset=0h]
0x14 ASI_FORMAT ASI Mode Control ASI_FORMAT (book=0x00 page=0x00 address=0x14) [reset=2h]
0x15 ASI_CHANNEL ASI Channel Control ASI_CHANNEL (book=0x00 page=0x00 address=0x15) [reset=0h]
0x16 ASI_OFFSET_1 ASI Offset ASI_OFFSET_1 (book=0x00 page=0x00 address=0x16) [reset=0h]
0x17 ASI_OFFSET_2 ASI Offset Second Slot ASI_OFFSET_2 (book=0x00 page=0x00 address=0x17) [reset=0h]
0x18 ASI_CFG_1 ASI Configuration ASI_CFG_1 (book=0x00 page=0x00 address=0x18) [reset=0h]
0x19 ASI_DIV_SRC ASI BDIV Clock Input ASI_DIV_SRC (book=0x00 page=0x00 address=0x19) [reset=0h]
0x1A ASI_BDIV ASI BDIV Configuration ASI_BDIV (book=0x00 page=0x00 address=0x1A) [reset=1h]
0x1B ASI_WDIV ASI WDIV Configuration ASI_WDIV (book=0x00 page=0x00 address=0x1B) [reset=40h]
0x1C PDM_CFG PDM Configuration PDM_CFG (book=0x00 page=0x00 address=0x1C) [reset=0h]
0x1D PDM_DIV PDM Divider Configuration PDM_DIV (book=0x00 page=0x00 address=0x1D) [reset=8h]
0x1E DSD_DIV DSD Divider Configuration DSD_DIV (book=0x00 page=0x00 address=0x1E) [reset=8h]
0x21 CLK_ERR_1 Clock Error and DSP memory Reload CLK_ERR_1 (book=0x00 page=0x00 address=0x21) [reset=3h]
0x22 CLK_ERR_2 Clock Error Configuration CLK_ERR_2 (book=0x00 page=0x00 address=0x22) [reset=3Fh]
0x23 IRQ_PIN_CFG Interrupt Pin Configuration IRQ_PIN_CFG (book=0x00 page=0x00 address=0x23) [reset=21h]
0x24 INT_CFG_1 Interrupt Configuration 1 INT_CFG_1 (book=0x00 page=0x00 address=0x24) [reset=0h]
0x25 INT_CFG_2 Interrupt Configuration 2 INT_CFG_2 (book=0x00 page=0x00 address=0x25) [reset=0h]
0x26 INT_DET_1 Interrupt Detected 1 INT_DET_1 (book=0x00 page=0x00 address=0x26) [reset=0h]
0x27 INT_DET_2 Interrupt Detected 2 INT_DET_2 (book=0x00 page=0x00 address=0x27) [reset=0h]
0x2A STATUS_POWER Status Block Power STATUS_POWER (book=0x00 page=0x00 address=0x2A) [reset=0h]
0x2D SAR_VBAT_MSB SAR VBAT Measurement MSB SAR_VBAT_MSB (book=0x00 page=0x00 address=0x2D) [reset=C0h]
0x2E SAR_VBAT_LSB SAR VBAT Measurement LSB SAR_VBAT_LSB (book=0x00 page=0x00 address=0x2E) [reset=0h]
0x31 DIE_TEMP_SENSOR Die Temperature Sensor DIE_TEMP_SENSOR (book=0x00 page=0x00 address=0x31) [reset=0h]
0x35 LOW_PWR_MODE Low Power Configuration LOW_PWR_MODE (book=0x00 page=0x00 address=0x35) [reset=0h]
0x36 PCM_RATE PCM Sample Rate PCM_RATE (book=0x00 page=0x00 address=0x36) [reset=32h]
0x4F CLOCK_ERR_CFG_1 Clock Error Configuration 1 CLOCK_ERR_CFG_1 (book=0x00 page=0x00 address=0x4F) [reset=0h]
0x50 CLOCK_ERR_CFG_2 Clock Error Configuration 2 CLOCK_ERR_CFG_2 (book=0x00 page=0x00 address=0x50) [reset=11h]
0x58 PROTECTION_CFG_1 Class PROTECTION_CFG_1 (book=0x00 page=0x00 address=0x58) [reset=3h]
0x7E CRC_CHECKSUM Checksum CRC_CHECKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
0x7F BOOK Book Selection BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]