ZHCSR17 january   2023 ADS9218

ADVANCE INFORMATION  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Diagrams
    9. 6.9  Typical Characteristics: ADS9218
    10. 6.10 Typical Characteristics: ADS9217
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Analog Input Bandwidth
      3. 7.3.3 ADC Transfer Function
      4. 7.3.4 Reference
        1. 7.3.4.1 Internal Reference Voltage
        2. 7.3.4.2 External Reference Voltage
      5. 7.3.5 Data Interface
        1. 7.3.5.1 Data Frame Width
        2. 7.3.5.2 Test Patterns for Data Interface
          1. 7.3.5.2.1 User-Defined Test Pattern
          2. 7.3.5.2.2 User-Defined Alternating Test Pattern
          3. 7.3.5.2.3 Ramp Test Pattern
      6. 7.3.6 ADC Sampling Clock Input
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Power-Down Options
    5. 7.5 Programming
      1. 7.5.1 Register Write
      2. 7.5.2 Register Read
      3. 7.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 7.5.3.1 Register Write With Daisy-Chain
        2. 7.5.3.2 Register Read With Daisy-Chain
    6. 7.6 Register Map
      1. 7.6.1 Register Bank 0
      2. 7.6.2 Register Bank 1
      3. 7.6.3 Register Bank 2
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Data Acquisition (DAQ) Circuit for ≤20-kHz Input Signal Bandwidth
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Data Acquisition (DAQ) Circuit for ≤100-kHz Input Signal Bandwidth
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curves
      3. 8.2.3 Data Acquisition (DAQ) Circuit for ≤1-MHz Input Signal Bandwidth
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

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机械数据 (封装 | 引脚)
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6.5 Electrical Characteristics

at AVDD_5V = 4.75 V to 5.25 V, AVDD_1V8 = 1.75 V to 1.85 V, DVDD_1V8 = 1.75 V to 1.85 V, internal VREF = 4.096 V, and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
IB Input bias current 0.5 TBD µA
IB Input bias current thermal drift 1 nA/℃
DC PERFORMANCE
Resolution No missing codes 18 Bits
DNL Differential nonlinearity –0.75 ±0.4 0.75 LSB
INL Integral nonlinearity –4 ±1 4 LSB
V(OS) Input offset error ±2 LSB
dVOS/dT Input offset error thermal drift ±1 ppm/°C
Offset error match V(OS) (ADC_A – ADC_B) 0.5 LSB
GE Gain error(1) –0.05 ±0.01 0.05 %FSR
dGE/dT Gain error thermal drift(2) ±1 ppm/°C
Gain error match GE (ADC_A – ADC_B) ±0.001 %FSR
AC PERFORMANCE
SINAD Signal-to-noise + distortion ratio fIN = 2 kHz 95 dB
fIN = 1 MHz 94
SNR Signal-to-noise ratio fIN = 2 kHz 95.1 dB
fIN = 1 MHz 94.1
THD Total harmonic distortion fIN = 2 kHz –115 dB
fIN = 1 MHz –102
SFDR Spurious-free dynamic range fIN = 2 kHz 120 dB
fIN = 1 MHz 102
Isolation crosstalk fIN = 1 MHz TBD dB
Aperture Jitter 0.3 psRMS
BW Input Bandwidth (–3-dB) ADS9218 90 MHz
ADS9217 45
COMMON-MODE OUTPUT BUFFER
VCMOUT Common-mode output voltage 2.4 V
Output current drive 0 5 μA
LVDS OUTPUT (CLKOUT, DOUTA, and DOUTB)
VODIFF Differential output voltage RL = 100Ω 250 350 450 mV
VOCM Output common-mode voltage RL = 100Ω 1.08 1.1 1.32 V
CMOS INPUTS (CS, SCLK, and SDI)
VIL Input low logic level –0.3 0.3 DVDD V
VIH Input high logic level 0.7 DVDD DVDD V
CMOS OUTPUT (SDO)
VOL Output low logic level IOL = 200 µA sink 0 0.2 DVDD V
VOH Output high logic level IOH = 200 µA source 0.8 DVDD DVDD V
POWER SUPPLY
IAVDD_5V Supply current from AVDD_5V Maximum throughput 36 TBD mA
No conversion, external reference TBD
IAVDD_1V8 Supply current from AVDD_1V8 Maximum throughput 67 TBD mA
No conversion, external reference TBD mA
IDVDD_1V8 Supply current from DVDD_1V8 Maximum throughput 34 TBD mA
No conversion, external reference 5 TBD
(1) These specifications include full temperature range variation but not the error contribution from internal reference.