ZHCSR17 january 2023 ADS9218
ADVANCE INFORMATION
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
CONVERSION CYCLE | |||||
fCYCLE | Sampling frequency | ADS9218 | 10 | MSPS | |
ADS9217 | 5 | ||||
tCYCLE | ADC cycle-time period | 1/fCYCLE | s | ||
tPL_SMPLCLK | Sample clock low time | 0.48 | 0.52 | tCYCLE | |
tPH_SMPLCLK | Sample clock high time | 0.48 | 0.52 | tCYCLE | |
fCLK | Maximum SCLK frequency | 10 | MHz | ||
tCLK | Minimum SCLK time period | 100 | ns | ||
SPI INTERFACE TIMINGS | |||||
thi_CSZ | Pulse duration: CS high | 220 | ns | ||
tPH_CK | SCLK high time | 0.48 | 0.52 | tCLK | |
tPL_CK | SCLK low time | 0.48 | 0.52 | tCLK | |
td_CSCK | Setup time: CS falling to the first SCLK rising edge | 20 | ns | ||
tsu_CKDI | Setup time: SDI data valid to the corresponding SCLK rising edge | 10 | ns | ||
tht_CKDI | Hold time: SCLK rising edge to corresponding data valid on SDI | 5 | ns | ||
td_CKCS | Delay time: last SCLK falling edge to CS rising | 5 | ns |