ZHCSR17 january   2023 ADS9218

ADVANCE INFORMATION  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Diagrams
    9. 6.9  Typical Characteristics: ADS9218
    10. 6.10 Typical Characteristics: ADS9217
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Analog Input Bandwidth
      3. 7.3.3 ADC Transfer Function
      4. 7.3.4 Reference
        1. 7.3.4.1 Internal Reference Voltage
        2. 7.3.4.2 External Reference Voltage
      5. 7.3.5 Data Interface
        1. 7.3.5.1 Data Frame Width
        2. 7.3.5.2 Test Patterns for Data Interface
          1. 7.3.5.2.1 User-Defined Test Pattern
          2. 7.3.5.2.2 User-Defined Alternating Test Pattern
          3. 7.3.5.2.3 Ramp Test Pattern
      6. 7.3.6 ADC Sampling Clock Input
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Power-Down Options
    5. 7.5 Programming
      1. 7.5.1 Register Write
      2. 7.5.2 Register Read
      3. 7.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 7.5.3.1 Register Write With Daisy-Chain
        2. 7.5.3.2 Register Read With Daisy-Chain
    6. 7.6 Register Map
      1. 7.6.1 Register Bank 0
      2. 7.6.2 Register Bank 1
      3. 7.6.3 Register Bank 2
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Data Acquisition (DAQ) Circuit for ≤20-kHz Input Signal Bandwidth
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Data Acquisition (DAQ) Circuit for ≤100-kHz Input Signal Bandwidth
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curves
      3. 8.2.3 Data Acquisition (DAQ) Circuit for ≤1-MHz Input Signal Bandwidth
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

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5 Pin Configuration and Functions

GUID-20210520-CA0I-6Q4Z-SHKF-KNQ8PHGJMJV6-low.svg Figure 5-1 RHA Package,6-mm × 6-mm, 40-Pin VQFN(Top View)
Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AINAM 4 I Negative analog input for ADC A.
AINAP 3 I Positive analog input for ADC A.
AINBM 8 I Negative analog input for ADC B.
AINBP 7 I Positive analog input for ADC B.
AVDD_1V8 13, 37 P 1.8-V analog power-supply pin.
AVDD_5V 1, 10 P 5-V analog power-supply pin.
CS 17 I Chip-select input pin for the configuration interface; active low.
DCLKM 23 O Negative differential data clock output. Connect a 100-Ω resistor between DCLKP and DCLKM close to the receiver.
DCLKP 24 O Positive differential data clock output. Connect a 100-Ω resistor between DCLKP and DCLKM close to the receiver.
DOUTAM 27 O Negative differential data output. Connect a 100-Ω resistor between DOUTAP and DOUTAM close to the receiver.
Transmits ADC A data in 2-lane mode.
Transmits ADC A and ADC B data in 1-lane mode.
DOUTAP 28 O Positive differential data output corresponding to ADC A. Connect a 100-Ω resistor between DOUTAP and DOUTAM close to the receiver.
Transmits ADC A data in 2-lane mode.
Transmits ADC A and ADC B data in 1-lane mode.
DOUTBM 25 O Positive differential data output corresponding to ADC B in 2-lane mode. Connect a 100-Ω resistor between DOUTBP and DOUTBM close to the receiver. Unused in 1-lane mode.
DOUTBP 26 O Negative differential data output corresponding to ADC B in 2-lane mode. Connect a 100-Ω resistor between DOUTBP and DOUTBM close to the receiver. Unused in 1-lane mode.
DVDD_1V8 14, 35, 36 P 1.8-V digital power supply.
FCLKM 29 O Negative differential data frame clock output. Connect a 100-Ω resistor between FCLKP and FCLKM close to the receiver.
FCLKP 30 O Positive differential data frame clock output. Connect a 100-Ω resistor between FCLKP and FCLKM close to the receiver.
GND 2, 9, 12, 15, 34, 38 P Ground.
PWDN 22 I Power-down control; active low.
Connect to DVDD_1V8 if unused.
REFIO 39 I/O Internal reference voltage output. External reference voltage input. Connect a 10-μF decoupling capacitor to REFM.
REFM 6, 11, 40 P Reference ground. Connect to GND.
RESET 21 I Reset input; active low.
Connect to DVDD_1V8 if unused.
SCLK 18 I Serial clock input for the configuration interface.
SDI 19 I Serial data input for the configuration interface.
SDO 20 O Serial data output for the configuration interface.
SMPL_CLKM 31 I ADC sampling clock input. Connect this pin to GND for the CMOS sampling clock.
SMPL_CLKP 32 I ADC sampling clock input. Clock input for the CMOS sampling clock.
SPI_EN 16 I Control to enable configuration of the SPI interface; active high.
Connect a pullup resistor to DVDD_1V8 to keep the configuration interface enabled.
Connect to GND if SPI configuration is unused.
SYNC 33 I Synchronization input for internal averaging filter.
Connect to GND if unused.
VCMOUT 5 O Common-mode voltage output. Use this output to set the common-mode voltage at the ADC inputs. Connect a 1-μF decoupling capacitor to GND.
(1) I = input, O = output, I/O = input or output, G = ground, P = power.