ZHCSR17 january   2023 ADS9218

ADVANCE INFORMATION  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Diagrams
    9. 6.9  Typical Characteristics: ADS9218
    10. 6.10 Typical Characteristics: ADS9217
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Analog Input Bandwidth
      3. 7.3.3 ADC Transfer Function
      4. 7.3.4 Reference
        1. 7.3.4.1 Internal Reference Voltage
        2. 7.3.4.2 External Reference Voltage
      5. 7.3.5 Data Interface
        1. 7.3.5.1 Data Frame Width
        2. 7.3.5.2 Test Patterns for Data Interface
          1. 7.3.5.2.1 User-Defined Test Pattern
          2. 7.3.5.2.2 User-Defined Alternating Test Pattern
          3. 7.3.5.2.3 Ramp Test Pattern
      6. 7.3.6 ADC Sampling Clock Input
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Power-Down Options
    5. 7.5 Programming
      1. 7.5.1 Register Write
      2. 7.5.2 Register Read
      3. 7.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 7.5.3.1 Register Write With Daisy-Chain
        2. 7.5.3.2 Register Read With Daisy-Chain
    6. 7.6 Register Map
      1. 7.6.1 Register Bank 0
      2. 7.6.2 Register Bank 1
      3. 7.6.3 Register Bank 2
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Data Acquisition (DAQ) Circuit for ≤20-kHz Input Signal Bandwidth
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Data Acquisition (DAQ) Circuit for ≤100-kHz Input Signal Bandwidth
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curves
      3. 8.2.3 Data Acquisition (DAQ) Circuit for ≤1-MHz Input Signal Bandwidth
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6.2 Register Bank 1

Figure 7-19 Register Bank 1 Map
ADD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
08h RESERVED TMP_REG_L8_3 TMP_REG_L8_2 TMP_REG_L8_1
0Bh RESERVED TMP_REG_LB_1
0Ch RESERVED TMP_REG_LC_1 RESERVED
0Dh RESERVED DATA_FORMAT TMP_REG_LD_2 TMP_REG_LD_1 RESERVED
11h RESERVED TMP_REG_L11_5 TMP_REG_L11_4 TMP_REG_L11_3 TMP_REG_L11_2 RESERVED TMP_REG_L11_1
12h RESERVED XOR_EN DATA_WIDTH DATA_LANES
13h RESERVED RAMP_INC_CH0 TEST_PAT_MODE_CH0 TEST_PAT_EN_CH0 RESERVED
14h TEST_PAT0_CH0
15h TEST_PAT1_CH0 TEST_PAT0_CH0
16h TEST_PAT1_CH0
18h RESERVED RAMP_INC_CH1 TEST_PAT_MODE_CH1 TEST_PAT_EN_CH1 RESERVED
19h TEST_PAT0_CH1
1Ah TEST_PAT1_CH1 TEST_PAT0_CH1
1Bh TEST_PAT1_CH1
33h RESERVED TMP_REG_L33_4 TMP_REG_L33_3 RESERVED TMP_REG_L33_2 RESERVED TMP_REG_L33_1 RESERVED
34h RESERVED TMP_REG_L34_3 RESERVED TMP_REG_L34_2 TMP_REG_L34_1
50h RESERVED TMP_REG_L50_3 TMP_REG_L50_2 TMP_REG_L50_1
51h RESERVED TMP_REG_L51_3 TMP_REG_L51_2 TMP_REG_L51_1
52h RESERVED TMP_REG_L52_2 TMP_REG_L52_1
C0h DCLK_CFG2 DCLK_CFG4 DCLK_CFG1 RESERVED PD_ADC
C1h RESERVED PD_REF RESERVED DATA_RATE RESERVED DCLK_CFG3

7.6.2.1 Register 8h (offset = 8h) [reset = 0h]

Figure 7-20 Register 8h
15 14 13 12 11 10 9 8
RESERVED TMP_REG_L8_3 TMP_REG_L8_2
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
TMP_REG_L8_2 TMP_REG_L8_1
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-21 Register 08 Field Descriptions
Bit Field Type Reset Description
15-15 RESERVED R/W 0h Reserved. Do not change from default reset value.
14-10 TMP_REG_L8_3 R/W 0h Temporary register.
0 : Normal device operation.
9-5 TMP_REG_L8_2 R/W 0h Temporary register.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
8 : Use for 40-bit 1-lane mode.
10 : Use for 48-bit 1-lane mode.
4-0 TMP_REG_L8_1 R/W 0h Temporary register.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
4 : Use for 40-bit 1-lane, and 48-bit 1-lane modes.

7.6.2.2 Register Bh (offset = Bh) [reset = 0h]

Figure 7-22 Register Bh
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED TMP_REG_LB_1
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-23 Register 0B Field Descriptions
Bit Field Type Reset Description
15-5 RESERVED R/W 0h Reserved. Do not change from default reset value.
4-0 TMP_REG_LB_1 R/W 0h Temporary register.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
6 : Use for 40-bit 1-lane, and 40-bit 1-lane modes.

7.6.2.3 Register Ch (offset = Ch) [reset = 0h]

Figure 7-24 Register Ch
15 14 13 12 11 10 9 8
RESERVED TMP_REG_LC_1
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
TMP_REG_LC_1 RESERVED
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-25 Register 0C Field Descriptions
Bit Field Type Reset Description
15-10 RESERVED R/W 0h Reserved. Do not change from default reset value.
9-5 TMP_REG_LC_1 R/W 0h Temporary register.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
1 : Use for 40-bit 1-lane, and 48-bit 1-lane modes.
4-0 RESERVED R/W 0h Reserved. Do not change from default reset value.

7.6.2.4 Register Dh (offset = Dh) [reset = 2002h]

Figure 7-26 Register Dh
15 14 13 12 11 10 9 8
RESERVED DATA_FORMAT TMP_REG_LD_2
R/W-0h R/W-1h R/W-0h
7 6 5 4 3 2 1 0
TMP_REG_LD_1 RESERVED
R/W-0h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-27 Register 0D Field Descriptions
Bit Field Type Reset Description
15-14 RESERVED R/W 0h Reserved. Do not change from default reset value.
13-13 DATA_FORMAT R/W 1h Select output data format for ADC conversion result.

0 : Straight binary
1 : 2's compliment
12-8 TMP_REG_LD_2 R/W 0h Temporary register. Write 00000b for normal device operation.
0 : Normal device operation.
7-7 TMP_REG_LD_1 R/W 0h Temporary register.
1 : Normal device operation.
6-0 RESERVED R/W 2h Reserved. Do not change from default reset value.

7.6.2.5 Register 11h (offset = 11h) [reset = A02h]

Figure 7-28 Register 11h
15 14 13 12 11 10 9 8
RESERVED TMP_REG_L11_5 TMP_REG_L11_4 TMP_REG_L11_3 TMP_REG_L11_2 RESERVED
R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-0h
7 6 5 4 3 2 1 0
RESERVED TMP_REG_L11_1
R/W-0h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-29 Register 11 Field Descriptions
Bit Field Type Reset Description
15-13 RESERVED R/W 0h Reserved. Do not change from default reset value.
12-12 TMP_REG_L11_5 R/W 0h Temporary register.
0 : Normal device operation.
11-11 TMP_REG_L11_4 R/W 1h Temporary register.
0 : Normal device operation.
10-10 TMP_REG_L11_3 R/W 0h Temporary register.
0 : Normal device operation.
9-9 TMP_REG_L11_2 R/W 1h Temporary register.
0 : Normal device operation.
8-3 RESERVED R/W 0h Reserved. Do not change from default reset value.
2-0 TMP_REG_L11_1 R/W 2h Temporary register. Write 100b for normal device operation.
4 : Normal device operation.

7.6.2.6 Register 12h (offset = 12h) [reset = Ah]

Figure 7-30 Register 12h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED XOR_EN DATA_WIDTH DATA_LANES
R/W-0h R/W-1h R/W-1h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-31 Register 12 Field Descriptions
Bit Field Type Reset Description
15-4 RESERVED R/W 0h Reserved. Do not change from default reset value.
3-3 XOR_EN R/W 1h Enables XOR function on ADC conversion result.
0 : XOR function is disabled
1 : Data output corresponding to ADC conversion result is launched as {D[23:5] xor D[4], D[4]}
2-1 DATA_WIDTH R/W 1h Select the output data frame width.
0 : 20-bit output frame. Use with 2-lane output mode (DATA_LANES = 0). ADC A and ADC B data are output in 20-bit format on DOUTA and DOUTB respectively.
1 : 24-bit output frame. Use with 2-lane output mode (DATA_LANES = 0). ADC A and ADC B data are output in 24-bit format on DOUTA and DOUTB respectively.
2 : 40-bit output frame. Use with 1-lane output mode (DATA_LANES = 1). ADC A and ADC B data are output in 20-bit format.
3 : 48-bit output frame. Use with 1-lane output mode (DATA_LANES = 1). ADC A and ADC B data are output in 24-bit format.
0-0 DATA_LANES R/W 0h Select number of LVDS output lanes
0 : 2-lane mode. ADC A data is output on DOUTA LVDS pair and ADC B data is output on DOUTB LVDS pair.
1 : 1-lane mode. ADC A data followed by ADC B data are output on DOUTA LVDS pair.

7.6.2.7 Register 13h (offset = 13h) [reset = 0h]

Figure 7-32 Register 13h
15 14 13 12 11 10 9 8
RESERVED
7 6 5 4 3 2 1 0
RAMP_INC_CH0 TEST_PAT_MODE_CH0 TEST_PAT_EN_CH0 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-33 Register 13 Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved. Do not change from default reset value.
7-4 RAMP_INC_CH0 R/W 0h Increment value for the ramp pattern output. The output ramp will increment by N+1 where N is the value configured in this register.
3-2 TEST_PAT_MODE_CH0 R/W 0h
0 : Fixed pattern as configured in TEST_PAT0_CH0 register
1 : Fixed pattern as configured in TEST_PAT1_CH0 register
2 : Ramp output
3 : Alternate fixed pattern output as configured in TEST_PAT0_CH0 and TEST_PAT1_CH0 registers
1-1 TEST_PAT_EN_CH0 R/W 0h Enable digital test pattern for data for data corresponding to channel 1, 2, 3, and 4.
0 : Normal operation. ADC data will be launched on the data interface.
1 : Digital test pattern will be launched corresponding to channels 1, 2, 3, and 4 on the data interface.
0-0 RESERVED R/W 0h Reserved bit. Do not change from default reset value.

7.6.2.8 Register 14h (offset = 14h) [reset = 0h]

Figure 7-34 Register 14h
15 14 13 12 11 10 9 8
TEST_PAT0_CH0[23:8]
R/W-0h
7 6 5 4 3 2 1 0
TEST_PAT0_CH0[23:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-35 Register 14 Field Descriptions
Bit Field Type Reset Description
15-0 TEST_PAT0_CH0[23:8] R/W 0h Test pattern 0 for channel 0.

7.6.2.9 Register 15h (offset = 15h) [reset = 0h]

Figure 7-36 Register 15h
15 14 13 12 11 10 9 8
TEST_PAT1_CH0[23:16]
R/W-0h
7 6 5 4 3 2 1 0
TEST_PAT0_CH0[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-37 Register 15 Field Descriptions
Bit Field Type Reset Description
15-8 TEST_PAT1_CH0[23:16] R/W 0h Test pattern 1 for channel 0.
7-0 TEST_PAT0_CH0[7:0] R/W 0h Test pattern 0 for channel 0.

7.6.2.10 Register 16h (offset = 16h) [reset = 0h]

Figure 7-38 Register 16h
15 14 13 12 11 10 9 8
TEST_PAT1_CH0[15:0]
R/W-0h
7 6 5 4 3 2 1 0
TEST_PAT1_CH0[15:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-39 Register 16 Field Descriptions
Bit Field Type Reset Description
15-0 TEST_PAT1_CH0[15:0] R/W 0h Test pattern 1 for channel 0.

7.6.2.11 Register 18h (offset = 18h) [reset = 0h]

Figure 7-40 Register 18h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RAMP_INC_CH1 TEST_PAT_MODE_CH1 TEST_PAT_EN_CH1 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-41 Register 18 Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved. Do not change from default reset value.
7-4 RAMP_INC_CH1 R/W 0h Increment value for the ramp pattern output. The output ramp will increment by N+1 where N is the value configured in this register.
3-2 TEST_PAT_MODE_CH1 R/W 0h
0 : Fixed pattern as configured in TEST_PAT0_CH1 register
1 : Fixed pattern as configured in TEST_PAT1_CH1 register
2 : Ramp output
3 : Alternate fixed pattern output as configured in TEST_PAT0_CH1 and TEST_PAT1_CH1 registers
1-1 TEST_PAT_EN_CH1 R/W 0h Enable digital test pattern for data corresponding to channels 5, 6, 7, and 8.
0 : Normal operation. ADC data will be launched on the data interface.
1 : Digital test pattern will be launched corresponding to channels 5, 6, 7, and 8 on the data interface.
0-0 RESERVED R/W 0h Reserved bit. Do not change from default reset value.

7.6.2.12 Register 19h (offset = 19h) [reset = 0h]

Figure 7-42 Register 19h
15 14 13 12 11 10 9 8
TEST_PAT0_CH1[23:8]
R/W-0h
7 6 5 4 3 2 1 0
TEST_PAT0_CH1[23:8]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-43 Register 19 Field Descriptions
Bit Field Type Reset Description
15-0 TEST_PAT0_CH1[23:8] R/W 0h Test pattern 0 for channel 1.

7.6.2.13 Register 1Ah (offset = 1Ah) [reset = 0h]

Figure 7-44 Register 1Ah
15 14 13 12 11 10 9 8
TEST_PAT1_CH1[23:16]
R/W-0h
7 6 5 4 3 2 1 0
TEST_PAT0_CH1[7:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-45 Register 1A Field Descriptions
Bit Field Type Reset Description
15-8 TEST_PAT1_CH1[23:16] R/W 0h Test pattern 1 for channel 1.
7-0 TEST_PAT0_CH1[7:0] R/W 0h Test pattern 0 for channel 1.

7.6.2.14 Register 1Bh (offset = 1Bh) [reset = 0h]

Figure 7-46 Register 1Bh
15 14 13 12 11 10 9 8
TEST_PAT1_CH1[15:0]
R/W-0h
7 6 5 4 3 2 1 0
TEST_PAT1_CH1[15:0]
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-47 Register 1B Field Descriptions
Bit Field Type Reset Description
15-0 TEST_PAT1_CH1[15:0] R/W 0h Test pattern 1 for channel 1.

7.6.2.15 Register 33h (offset = 33h) [reset = 0h]

Figure 7-48 Register 33h
15 14 13 12 11 10 9 8
RESERVED TMP_REG_L33_4 TMP_REG_L33_3 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED TMP_REG_L33_2 RESERVED TMP_REG_L33_1 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-49 Register 33 Field Descriptions
Bit Field Type Reset Description
15-15 RESERVED R/W 0h Reserved. Do not change from default reset value.
14-14 TMP_REG_L33_4 R/W 0h Temporary register.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
1 : Use for 40-bit 1-lane, and 48-bit 1-lane modes.
13-13 TMP_REG_L33_3 R/W 0h Temporary register in the user address space.Write 1b to this register for normal device operation.
0 : Not recommended
1 : Normal device operation
12-7 RESERVED R/W 0h Reserved. Do not change from default reset value.
6-6 TMP_REG_L33_2 R/W 0h Temporary register in the user address space.Write 1b to this register for normal device operation.
0 : Not recommended.
1 : Normal device operation.
5-4 RESERVED R/W 0h Reserved. Do not change from default reset value.
3-3 TMP_REG_L33_1 R/W 0h Temporary register in the user address space.Write 1b to this register for normal device operation.
0 : Not recommended.
1 : Normal device operation.
2-0 RESERVED R/W 0h Reserved. Do not change from default reset value.

7.6.2.16 Register 34h (offset = 34h) [reset = 0h]

Figure 7-50 Register 34h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED TMP_REG_L34_3 RESERVED TMP_REG_L34_2 TMP_REG_L34_1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-51 Register 34 Field Descriptions
Bit Field Type Reset Description
15-5 RESERVED R/W 0h Reserved. Do not change from default reset value.
4-4 TMP_REG_L34_3 R/W 0h Temporary register.
0 : Not recommended.
1 : Recommended. Normal device operation.
3-2 RESERVED R/W 0h Reserved. Do not change from default reset value.
1-1 TMP_REG_L34_2 R/W 0h Temporary register.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
1 : Use for 48-bit 1-lane, and 40-bit 1-lane modes.
0-0 TMP_REG_L34_1 R/W 0h Temporary register.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
1 : Use for 40-bit 1-lane, and 48-bit 1-lane modes.

7.6.2.17 Register 50h (offset = 50h) [reset = 0h]

Figure 7-52 Register 50h
15 14 13 12 11 10 9 8
RESERVED TMP_REG_L50_3 TMP_REG_L50_2
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
TMP_REG_L50_2 TMP_REG_L50_1
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-53 Register 50 Field Descriptions
Bit Field Type Reset Description
15-15 RESERVED R/W 0h Reserved. Do not change from default reset value.
14-10 TMP_REG_L50_3 R/W 0h Temporary register. Write 00000b for normal device operation.
0 : Use for 20-bit 2-lane, 24-bit 2-lane, and 40-bit 1-lane modes.
10 : Use for 48-bit 1-lane mode.
9-5 TMP_REG_L50_2 R/W 0h Temporary register.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
6 : Use for 40-bit 1-lane mode, and 48-bit 1-lane modes.
4-0 TMP_REG_L50_1 R/W 0h Temporary register.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
4 : Use for 40-bit 1-lane mode, and 48-bit 1-lane modes.

7.6.2.18 Register 51h (offset = 51h) [reset = 0h]

Figure 7-54 Register 51h
15 14 13 12 11 10 9 8
RESERVED TMP_REG_L51_3 TMP_REG_L51_2
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
TMP_REG_L51_2 TMP_REG_L51_1
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-55 Register 51 Field Descriptions
Bit Field Type Reset Description
15-15 RESERVED R/W 0h Reserved. Do not change from default reset value.
14-10 TMP_REG_L51_3 R/W 0h Temporary register.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
4 : Use for 40-bit 1-lane mode, and 48-bit 1-lane modes.
9-5 TMP_REG_L51_2 R/W 0h Temporary register.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
4 : Use for 40-bit 1-lane mode, and 48-bit 1-lane modes.
4-0 TMP_REG_L51_1 R/W 0h Temporary register.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
4 : Use for 40-bit 1-lane, and 48-bit 1-lane modes.

7.6.2.19 Register 52h (offset = 52h) [reset = 0h]

Figure 7-56 Register 52h
15 14 13 12 11 10 9 8
RESERVED TMP_REG_L52_2
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
TMP_REG_L52_2 TMP_REG_L52_1
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-57 Register 52 Field Descriptions
Bit Field Type Reset Description
15-10 RESERVED R/W 0h Reserved. Do not change from default reset value.
9-5 TMP_REG_L52_2 R/W 0h Temporary register. Write 00000b for normal device operation.
0 : Normal device operation.
4-0 TMP_REG_L52_1 R/W 0h Temporary register. Write 00000b for normal device operation.
0 : Normal device operation.

7.6.2.20 Register C0h (offset = C0h) [reset = 0h]

Figure 7-58 Register C0h
15 14 13 12 11 10 9 8
DCLK_CFG2 DCLK_CFG4 DCLK_CFG1 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED PD_ADC
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-59 Register C0 Field Descriptions
Bit Field Type Reset Description
15-14 DCLK_CFG2 R/W 0h Data clock configuration 2.
1 : Normal device operation.
13-12 DCLK_CFG4 R/W 0h Data clock configuration 4.
0 : Use for 24-bit 2-lane, and 20-bit 2-lane modes.
1 : Use for 48-bit 1-lane, and 40-bit 1-lane modes.
11-10 DCLK_CFG1 R/W 0h Data clock configuration 1.
0 : Use for 40-bit 1-lane mode.
1 : Use for 24-bit 2-lane, 20-bit 2-lane, and 48-bit 1-lane modes.
9-2 RESERVED R/W 0h Reserved. Do not change from default reset value.
1-0 PD_ADC R/W 0h Power-down control for ADC channels
0 : Normal device operation.
1 : ADC A power down.
2 : ADC B power down.
3 : ADC A and ADC B power down.

7.6.2.21 Register C1h (offset = C1h) [reset = 0h]

Figure 7-60 Register C1h
15 14 13 12 11 10 9 8
RESERVED PD_REF RESERVED DATA_RATE
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED RESERVED RESERVED RESERVED DCLK_CFG3
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 7-61 Register C1 Field Descriptions
Bit Field Type Reset Description
15-12 RESERVED R/W 0h Reserved. Do not change from default reset value.
11-11 PD_REF R/W 0h ADC reference selection
0 : Internal reference enabled
1 : Internal reference disabled. Connect external reference at REFIO pin.
10-9 RESERVED R/W 0h Reserved. Do not change from default reset value.
8-8 DATA_RATE R/W 0h Select data rate for the data interface.
0 : Double Data Rate (DDR)
1 : Single Data Rate (SDR)
7-4 RESERVED R/W 0h Reserved. Do not change from default reset value.
3-0 DCLK_CFG3 R/W 0h Data clock configuration 3.
8 : Use for 24-bit 2-lane, and 48-bit 1-lane modes.
9 : Use for 20-bit 2-lane, and 40-bit 1-lane modes.