ZHCSR17 january 2023 ADS9218
ADVANCE INFORMATION
Use a low jitter external clock with a high slew rate to maximize the ADC SNR performance. The ADS921x can be operated using a single-ended clock input where the single-ended clock consumes less power consumption. Clock amplitude impacts the ADC aperture jitter and consequently the SNR. For maximum SNR performance, a large clock signal with fast slew rates must be provided.
The sampling clock must be a free-running continuous clock. The ADC generates valid output data, a data clock, and a frame clock tPU_SMPL_CLK, as specified in the Switching Characteristics section after a free-running sampling clock is applied. ADC output data, the data clock, and the frame clock are invalid when the sampling clock is stopped.
Figure 7-5 shows a diagram of the single-ended sampling clock. Connect a single-ended sampling clock to SMPL_CLKP and connect SMPL_CLKM to ground.