ZHCSQZ8A May   2022  – December 2022 ADS1285

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: 1.65 V ≤ IOVDD ≤ 1.95 V and 2.7 V ≤ IOVDD ≤ 3.6 V
    7. 6.7 Switching Characteristics: 1.65V ≤ IOVDD ≤ 1.95V and 2.7 V ≤ IOVDD ≤ 3.6 V
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 PGA and Buffer
        1. 8.3.2.1 Programmable Gain Amplifier (PGA)
        2. 8.3.2.2 Buffer Operation (PGA Bypass)
      3. 8.3.3 Voltage Reference Input
      4. 8.3.4 IOVDD Power Supply
      5. 8.3.5 Modulator
        1. 8.3.5.1 Modulator Overdrive
      6. 8.3.6 Digital Filter
        1. 8.3.6.1 Sinc Filter Section
        2. 8.3.6.2 FIR Filter Section
        3. 8.3.6.3 Group Delay and Step Response
          1. 8.3.6.3.1 Linear Phase Response
          2. 8.3.6.3.2 Minimum Phase Response
        4. 8.3.6.4 HPF Stage
      7. 8.3.7 Clock Input
      8. 8.3.8 GPIO
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
      2. 8.4.2 Power-Down Mode
      3. 8.4.3 Reset
      4. 8.4.4 Synchronization
        1. 8.4.4.1 Pulse-Sync Mode
        2. 8.4.4.2 Continuous-Sync Mode
      5. 8.4.5 Sample Rate Converter
      6. 8.4.6 Offset and Gain Calibration
        1. 8.4.6.1 OFFSET Register
        2. 8.4.6.2 GAIN Register
        3. 8.4.6.3 Calibration Procedure
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Input (DIN)
        4. 8.5.1.4 Data Output (DOUT)
        5. 8.5.1.5 Data Ready (DRDY)
      2. 8.5.2 Conversion Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1  Single Byte Command
        2. 8.5.3.2  WAKEUP: Wake Command
        3. 8.5.3.3  STANDBY: Software Power-Down Command
        4. 8.5.3.4  SYNC: Synchronize Command
        5. 8.5.3.5  RESET: Reset Command
        6. 8.5.3.6  Read Data Direct
        7. 8.5.3.7  RDATA: Read Conversion Data Command
        8. 8.5.3.8  RREG: Read Register Command
        9. 8.5.3.9  WREG: Write Register Command
        10. 8.5.3.10 OFSCAL: Offset Calibration Command
        11. 8.5.3.11 GANCAL: Gain Calibration Command
    6. 8.6 Register Map
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1 ID/SYNC: Device ID, SYNC Register (Address = 00h) [Reset = xxxx0000b]
        2. 8.6.1.2 CONFIG0: Configuration Register 0 (Address = 01h) [Reset = 12h]
        3. 8.6.1.3 CONFIG1: Configuration Register 1 (Address = 02h) [Reset = 00h]
        4. 8.6.1.4 HPF0, HPF1: High-Pass Filter Registers (Address = 03h, 04h) [Reset = 32h, 03h]
        5. 8.6.1.5 OFFSET0, OFFSET1, OFFSET2: Offset Calibration Registers (Address = 05h, 06h, 07h) [Reset = 00h, 00h, 00h]
        6. 8.6.1.6 GAIN0, GAIN1, GAIN2: Gain Calibration Registers (Address = 08h, 09h, 0Ah) [Reset = 00h, 00h, 40h]
        7. 8.6.1.7 GPIO: Digital Input/Output Register (Address = 0Bh) [Reset = 000xx000b]
        8. 8.6.1.8 SRC0, SRC1: Sample Rate Converter Registers (Address = 0Ch, 0Dh) [Reset = 00h, 80h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Analog Power Supplies
      2. 9.3.2 Digital Power Supply
      3. 9.3.3 Grounds
      4. 9.3.4 Thermal Pad
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RHB|32
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

minimum and maximum specifications over –40°C to +85°C; typical specifications are at 25°C; all specifications are at AVDD1 = 5 V, AVDD2 = 2.5 V to 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREFP = 4.096 V, VREFN = 0 V,  VCM = 2.5 V, PGA gain = 1, fCLK = 8.192 MHz (4.096 MHz low-power mode) and fDATA = 500 SPS (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Input mux on-resistance Input 1 to input 2 cross connection 60 Ω
PGA OPERATION
IB PGA Input bias current High-power mode 45 nA
IOS PGA Input offset current High-power mode ±3 nA
PGA Gain 1, 2, 4, 8, 16, 32, 64 V/V
en-PGA PGA Input voltage noise density High-power mode PGA Gain = 16 5.5 nV/√Hz
Mid-power mode 7
Low-power mode 7
in-PGA PGA Input current noise density Differential 2.5 pA/√Hz
Antialias filter frequency 30 kHz
BUFFER OPERATION
IB Input current High-power mode VIN = 2.5 V ±1.2 µA
Mid-power mode ±1.2
Low-power mode ±0.3
DC PERFORMANCE
en Noise  See Noise Performance section for details
VOS Offset error PGA operation –350/gain - 10 ±30/gain + 5 350/gain + 10 µV
Buffer operation –600 ±50 600
After calibration ±1
Offset error drift PGA operation 0.5/gain µV/°C
Buffer operation 1
Gain error PGA operation, gain = 1 –0.05% ±0.02% 0.05%
After calibration 2 ppm
Buffer operation –0.07% ±0.05% 0.07%
Gain match Relative to PGA gain = 1 –0.2% ±0.06% 0.2%
Gain drift All PGA gains 2 ppm/°C
CMRR Common-mode rejection ratio f = 60 Hz 104 120 dB
PSRR Power-supply rejection ratio AVDD2 At dc 80 95 dB
AVSS, AVDD1 85 110 dB
IOVDD 100 120 dB
AC PERFORMANCE
en-MOD Modulator voltage noise density VREF = 4.096 V 25 nV/√Hz
THD Total harmonic distortion High-power mode,
VREF = 2.5 V,
AVDD1 = 3.3 V,
AVSS = 0 V,
fIN = 31.25 Hz,
VIN = –0.5 dBFS		 Buffer operation –123 -114 dB
PGA gain = 2 –119
PGA gain = 4 –125 -116
PGA gain = 8 –124
PGA gain = 16 –123 -116
PGA gain = 32 and 64 –125
Mid-power mode,
VREF = 2.5 V,
AVDD1 = 3.3 V,
AVSS = 0 V,
fIN = 31.25 Hz,
VIN = –0.5 dBFS		 Buffer operation –122 -113 dB
PGA gain = 2 –120
PGA gain = 4 –125 -118
PGA gain = 8 –124
PGA gain = 16 –123 -115
PGA gain = 32 and 64 –125
Low-power mode,
VREF = 2.5 V,
AVDD1 = 3.3 V,
AVSS = 0 V,
fIN = 31.25 Hz,
VIN = –0.5 dBFS		 Buffer operation –124 -117 dB
PGA gain = 2 –122
PGA gain = 4 –124 -116
PGA gain = 8 –125
PGA gain = 16 –123 -115
PGA gain = 32 and 64 –124
High-power mode,
VREF = 4.096 V,
AVDD1 = 5 V,
AVSS = 0 V,
fIN = 31.25 Hz,
VIN = –0.5 dBFS		 Buffer operation –119 -114 dB
PGA gain = 1 –119 -111
PGA gain = 2 –125
PGA gain = 4 –122 -114
PGA gain = 8 –118
PGA gain = 16 –117 -111
PGA gain = 32 and 64 –125
Mid-power mode,
VREF = 4.096 V,
AVDD1 = 5 V,
AVSS = 0 V,
fIN = 31.25 Hz,
VIN = –0.5 dBFS		 Buffer operation –119 -112 dB
PGA gain = 1 –119 -111
PGA gain = 2 –125
PGA gain = 4 –124 -115
PGA gain = 8 –119
PGA gain = 16 –117 -111
PGA gain = 32 and 64 –124
Low-power mode,
VREF = 4.096 V,
AVDD1 = 5 V,
AVSS = 0 V,
fIN = 31.25 Hz,
VIN = –0.5 dBFS		 Buffer operation –123 -117 dB
PGA gain = 1 –121 -115
PGA gain = 2 –124
PGA gain = 4 –125 -115
PGA gain = 8 –122
PGA gain = 16 –121 -113
PGA gain = 32 and 64 –123
SFDR Spurious-free dynamic range  fIN = 31.25 Hz, VIN = –0.5 dBFS 115 dB
Crosstalk  fIN = 31.25 Hz, VIN = –0.5 dBFS –140 dB
VOLTAGE REFERENCE INPUT
Reference input current High-power mode 110 µA/V
Mid-power mode 110
Low-power  mode 80
FIR DIGITAL FILTER
fDATA Data rate High-power mode 250 4000 SPS
Mid-power mode 250 4000
Low-power mode 125 2000
Pass-band ripple –0.003 0.003 dB
Pass-band (–0.01 dB) 0.375 × fDATA Hz
Bandwidth (–3 dB) 0.413 × fDATA Hz
Stop band 0.5 × fDATA Hz
Stop-band attenuation (1) 135 dB
Group delay Minimum phase filter, at dc 5 / fDATA s
Linear phase filter 31/ fDATA
Settling time (latency) Minimum phase filter 62 / fDATA s
Linear phase filter 62 / fDATA
IIR DIGITAL FILTER
High-pass corner frequency 0.1 10 Hz
SAMPLE RATE CONVERTER
Clock compensation range –244 244 ppm of fCLK
Resolution 7.45 ppb of fCLK
DIGITAL INPUT/OUTPUT
VOH High-level output voltage IOH = 1 mA 0.8 × IOVDD V
VOL Low-level output voltage IOL = –1 mA 0.2 × IOVDD V
Ilkg Input leakage –1 1 μA
POWER SUPPLY
IAVDD1,
IAVSS		 AVDD1, AVSS current High-power mode
AVDD1 = 3.3 V		 PGA operation 1.4 mA
Buffer operation 0.25
Mid-power mode
AVDD1 = 3.3 V		 PGA operation 0.85 mA
Buffer operation 0.25
Low-power mode
AVDD1 = 3.3 V		 PGA operation 0.8 mA
Buffer operation 0.2
High-power mode
AVDD1 = 5 V		 PGA operation 1.5 1.85 mA
Buffer operation 0.35 0.45
Mid-power mode
AVDD1 = 5 V		 PGA operation 0.9 1.2 mA
Buffer operation 0.35 0.45
Low-power mode
AVDD1 = 5 V		 PGA operation 0.85 1.1 mA
Buffer operation 0.25 0.45
Power-down mode 1 5 µA
IAVDD2 AVDD2 current High-power mode AVDD2 = 2.5 V 1.2 1.5 mA
Mid-power mode 1.2 1.5
Low-power mode 0.7 0.85
Power-down mode 1 5 µA
IIOVDD IOVDD current High-power mode 0.43 0.6 mA
Mid-power mode 0.43 0.6
Low-power mode 0.24 0.4
Power-down mode 1 10 μA
Standby mode 200
IOVDD additional current High-power mode Sample rate converter operation 1.2 mA
Mid-power mode 1.2
Low-power mode 0.6
Pd Power dissipation (2) High-power mode
AVDD1 = 3.3 V
AVDD2 = 2.5 V		 PGA operation 8.3 mW
Buffer operation 4.5
Mid-power mode
AVDD1 = 3.3 V
AVDD2 = 2.5 V		 PGA operation 6.5 mW
Buffer operation 4.5
Low-power mode
AVDD1 = 3.3 V
AVDD2 = 2.5 V		 PGA operation 4.8 mW
Buffer operation 2.8
High-power mode
AVDD1 = 5 V
AVDD2 = 2.5 V		 PGA operation 11.5 14.1 mW
Buffer operation 5.3 6.7
Mid-power mode
AVDD1 = 5 V
AVDD2 = 2.5 V		 PGA operation 8.3 10.8 mW
Buffer operation 5.3 6.7
Low-power mode
AVDD1 = 5 V
AVDD2 = 2.5 V		 PGA operation 6.4 8.4 mW
Buffer operation 3.4 5.1
(1) Input frequencies at N × 32 kHz (16 kHz low-power mode) ± fDATA / 2 (where N = 1, 2, 3...) intermodulate with the chopper clock. At these frequencies stop band attenuation = –90 dBFS (typ).
(2) Excluding current consumed by the voltage reference input or by sample rate converter operation. See voltage reference input current and IOVDD current of sample rate converter operation.