ZHCSFP7A November   2016  – February 2017 TAS2557

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. 说明(续)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  I2C Timing Requirements
    7. 8.7  SPI Timing Requirements
    8. 8.8  I2S/LJF/RJF Timing in Master Mode
    9. 8.9  I2S/LJF/RJF Timing in Slave Mode
    10. 8.10 DSP Timing in Master Mode
    11. 8.11 DSP Timing in Slave Mode
    12. 8.12 Typical Characteristics
  9. Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  General I2C Operation
      2. 10.3.2  Single-Byte and Multiple-Byte Transfers
      3. 10.3.3  Single-Byte Write
      4. 10.3.4  Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 10.3.5  Single-Byte Read
      6. 10.3.6  Multiple-Byte Read
      7. 10.3.7  General SPI Operation
      8. 10.3.8  Class-D Edge Rate Control
      9. 10.3.9  IV Sense
      10. 10.3.10 Battery Tracking AGC
      11. 10.3.11 Boost Control
        1. 10.3.11.1 Boost Mode
        2. 10.3.11.2 Configurable Boost Current Limit (ILIM)
      12. 10.3.12 Thermal Fold-back
      13. 10.3.13 Fault Protection
        1. 10.3.13.1 Speaker Over-Current
        2. 10.3.13.2 Analog Under-Voltage
        3. 10.3.13.3 Die Over-Temperature
        4. 10.3.13.4 Clocking Faults
      14. 10.3.14 Brownout
      15. 10.3.15 Spread Spectrum vs Synchronized
      16. 10.3.16 IRQs and Flags
      17. 10.3.17 Software Reset
      18. 10.3.18 PurePath Console 3 Software TAS2557 Application
    4. 10.4 Device Functional Modes
      1. 10.4.1 Audio Digital I/O Interface
        1. 10.4.1.1 I2S Mode
        2. 10.4.1.2 DSP Mode
        3. 10.4.1.3 Right-Justified Mode (RJF)
        4. 10.4.1.4 Left-Justified Mode (LJF)
      2. 10.4.2 Mono PCM Mode
      3. 10.4.3 Stereo Application Example - TDM Mode
    5. 10.5 Operational Modes
      1. 10.5.1 Hardware Shutdown
      2. 10.5.2 Software Shutdown
      3. 10.5.3 Low Power Sleep
      4. 10.5.4 Software Reset
      5. 10.5.5 Device Processing Modes
        1. 10.5.5.1 Mode 1 - PCM input playback only
        2. 10.5.5.2 Mode 2 - PCM input playback + PCM IVsense output
        3. 10.5.5.3 Mode 3 - Smart Amp Mode
    6. 10.6 Programming
      1. 10.6.1 Code Loading and CRC check
      2. 10.6.2 Device Power Up and Unmute Sequence
      3. 10.6.3 Device Mute and Power Down Sequence
  11. 11Applications and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 Detailed Design Procedure
          1. 11.2.1.1.1 Mono/Stereo Configuration
          2. 11.2.1.1.2 Boost Converter Passive Devices
          3. 11.2.1.1.3 EMI Passive Devices
          4. 11.2.1.1.4 Miscellaneous Passive Devices
      2. 11.2.2 Application Performance Plots
    3. 11.3 Initialization Set Up
  12. 12Power Supply Recommendations
    1. 12.1 Power Supplies
    2. 12.2 Power Supply Sequencing
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Register Map
    1. 14.1 Register Map Summary
      1. 14.1.1 Register Summary Table Book=0x00 Page=0x00
      2. 14.1.2 Register Summary Table Book=0x00 Page=0x01
      3. 14.1.3 Register Summary Table Book=0x00 Page=0x02
    2. 14.2 Register Maps
      1. 14.2.1   PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
      2. 14.2.2   RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
      3. 14.2.3   POWER_1 (book=0x00 page=0x00 address=0x04) [reset=0h]
      4. 14.2.4   POWER_2 (book=0x00 page=0x00 address=0x05) [reset=0h]
      5. 14.2.5   SPK_GAIN_EDGE (book=0x00 page=0x00 address=0x06) [reset=0h]
      6. 14.2.6   MUTE (book=0x00 page=0x00 address=0x07) [reset=0h]
      7. 14.2.7   SNS_CTRL (book=0x00 page=0x00 address=0x08) [reset=0h]
      8. 14.2.8   BOOST_CTRL_1 (book=0x00 page=0x00 address=0x09) [reset=0h]
      9. 14.2.9   SAR_CTRL_2 (book=0x00 page=0x00 address=0x14) [reset=32h]
      10. 14.2.10  SAR_CTRL_3 (book=0x00 page=0x00 address=0x15) [reset=4h]
      11. 14.2.11  SAR_VBAT_MSB (book=0x00 page=0x00 address=0x16) [reset=0h]
      12. 14.2.12  SAR_VBAT_LSB (book=0x00 page=0x00 address=0x17) [reset=0h]
      13. 14.2.13  SAR_VBST_MSB (book=0x00 page=0x00 address=0x18) [reset=0h]
      14. 14.2.14  SAR_VBST_LSB (book=0x00 page=0x00 address=0x19) [reset=0h]
      15. 14.2.15  SAR_TMP1_MSB (book=0x00 page=0x00 address=0x1A) [reset=0h]
      16. 14.2.16  SAR_TMP1_LSB (book=0x00 page=0x00 address=0x1B) [reset=0h]
      17. 14.2.17  SAR_TMP2_MSB (book=0x00 page=0x00 address=0x1C) [reset=0h]
      18. 14.2.18  SAR_TMP2_LSB (book=0x00 page=0x00 address=0x1D) [reset=0h]
      19. 14.2.19  CRC_CHECKSUM (book=0x00 page=0x00 address=0x20) [reset=0h]
      20. 14.2.20  CRC_RESET (book=0x00 page=0x00 address=0x21) [reset=0h]
      21. 14.2.21  DSP_CTRL (book=0x00 page=0x00 address=0x22) [reset=1h]
      22. 14.2.22  SSM_CTRL (book=0x00 page=0x00 address=0x28) [reset=0h]
      23. 14.2.23  ASI_CTRL_1 (book=0x00 page=0x00 address=0x2A) [reset=0h]
      24. 14.2.24  BOOST_CTRL_2 (book=0x00 page=0x00 address=0x2B) [reset=3h]
      25. 14.2.25  CLOCK_CTRL_1 (book=0x00 page=0x00 address=0x2C) [reset=0h]
      26. 14.2.26  CLOCK_CTRL_2 (book=0x00 page=0x00 address=0x2D) [reset=17h]
      27. 14.2.27  CLOCK_CTRL_3 (book=0x00 page=0x00 address=0x2E) [reset=0h]
      28. 14.2.28  ASI_CTRL_2 (book=0x00 page=0x00 address=0x2F) [reset=0h]
      29. 14.2.29  CLOCK_CTRL_4 (book=0x00 page=0x00 address=0x32) [reset=0h]
      30. 14.2.30  DEBUG_1 (book=0x00 page=0x00 address=0x35) [reset=0h]
      31. 14.2.31  POWER_STATUS (book=0x00 page=0x00 address=0x64) [reset=0h]
      32. 14.2.32  DSP_BOOT_STATUS (book=0x00 page=0x00 address=0x65) [reset=0h]
      33. 14.2.33  INT_DET_1 (book=0x00 page=0x00 address=0x68) [reset=0h]
      34. 14.2.34  INT_DET_2 (book=0x00 page=0x00 address=0x6C) [reset=0h]
      35. 14.2.35  LOW_POWER (book=0x00 page=0x00 address=0x79) [reset=0h]
      36. 14.2.36  BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
      37. 14.2.37  PAGE (book=0x00 page=0x01 address=0x00) [reset=1h]
      38. 14.2.38  ASI1_FORMAT (book=0x00 page=0x01 address=0x01) [reset=10h]
      39. 14.2.39  ASI1_OFFSET_1 (book=0x00 page=0x01 address=0x03) [reset=0h]
      40. 14.2.40  ASI1_BUSKEEP (book=0x00 page=0x01 address=0x05) [reset=0h]
      41. 14.2.41  ASI1_BCLK (book=0x00 page=0x01 address=0x08) [reset=0h]
      42. 14.2.42  ASI1_WCLK (book=0x00 page=0x01 address=0x09) [reset=8h]
      43. 14.2.43  ASI1_DIN_DOUT (book=0x00 page=0x01 address=0x0C) [reset=0h]
      44. 14.2.44  ASI1_BDIV_CLK (book=0x00 page=0x01 address=0x0D) [reset=1h]
      45. 14.2.45  ASI1_BDIV_RATIO (book=0x00 page=0x01 address=0x0E) [reset=2h]
      46. 14.2.46  ASI1_WDIV_RATIO (book=0x00 page=0x01 address=0x0F) [reset=20h]
      47. 14.2.47  ASI1_CLK_OUT (book=0x00 page=0x01 address=0x10) [reset=0h]
      48. 14.2.48  ASI2_FORMAT (book=0x00 page=0x01 address=0x15) [reset=10h]
      49. 14.2.49  ASI2_OFFSET_1 (book=0x00 page=0x01 address=0x17) [reset=0h]
      50. 14.2.50  ASI2_BUSKEEP (book=0x00 page=0x01 address=0x19) [reset=0h]
      51. 14.2.51  ASI2_BCLK (book=0x00 page=0x01 address=0x1C) [reset=20h]
      52. 14.2.52  ASI2_WCLK (book=0x00 page=0x01 address=0x1D) [reset=28h]
      53. 14.2.53  ASI2_DIN_DOUT (book=0x00 page=0x01 address=0x20) [reset=38h]
      54. 14.2.54  ASI2_BDIV_CLK (book=0x00 page=0x01 address=0x21) [reset=1h]
      55. 14.2.55  ASI2_BDIV_RATIO (book=0x00 page=0x01 address=0x22) [reset=2h]
      56. 14.2.56  ASI2_WDIV_RATIO (book=0x00 page=0x01 address=0x23) [reset=20h]
      57. 14.2.57  ASI2_CLK_OUT (book=0x00 page=0x01 address=0x24) [reset=33h]
      58. 14.2.58  GPIO1_PIN (book=0x00 page=0x01 address=0x3D) [reset=1h]
      59. 14.2.59  GPIO2_PIN (book=0x00 page=0x01 address=0x3E) [reset=1h]
      60. 14.2.60  GPIO3_PIN (book=0x00 page=0x01 address=0x3F) [reset=10h]
      61. 14.2.61  GPIO4_PIN (book=0x00 page=0x01 address=0x40) [reset=7h]
      62. 14.2.62  GPIO5_PIN (book=0x00 page=0x01 address=0x41) [reset=0h]
      63. 14.2.63  GPIO6_PIN (book=0x00 page=0x01 address=0x42) [reset=0h]
      64. 14.2.64  GPIO7_PIN (book=0x00 page=0x01 address=0x43) [reset=0h]
      65. 14.2.65  GPIO8_PIN (book=0x00 page=0x01 address=0x44) [reset=0h]
      66. 14.2.66  GPIO9_PIN (book=0x00 page=0x01 address=0x45) [reset=0h]
      67. 14.2.67  GPIO10_PIN (book=0x00 page=0x01 address=0x46) [reset=0h]
      68. 14.2.68  GPI_PIN (book=0x00 page=0x01 address=0x4D) [reset=0h]
      69. 14.2.69  GPIO_HIZ_1 (book=0x00 page=0x01 address=0x4F) [reset=0h]
      70. 14.2.70  GPIO_HIZ_2 (book=0x00 page=0x01 address=0x50) [reset=0h]
      71. 14.2.71  GPIO_HIZ_3 (book=0x00 page=0x01 address=0x51) [reset=0h]
      72. 14.2.72  GPIO_HIZ_4 (book=0x00 page=0x01 address=0x52) [reset=0h]
      73. 14.2.73  GPIO_HIZ_5 (book=0x00 page=0x01 address=0x53) [reset=0h]
      74. 14.2.74  BIT_BANG_OUT1 (book=0x00 page=0x01 address=0x58) [reset=0h]
      75. 14.2.75  BIT_BANG_OUT2 (book=0x00 page=0x01 address=0x59) [reset=0h]
      76. 14.2.76  BIT_BANG_IN1 (book=0x00 page=0x01 address=0x5A) [reset=0h]
      77. 14.2.77  BIT_BANG_IN2 (book=0x00 page=0x01 address=0x5B) [reset=0h]
      78. 14.2.78  BIT_BANG_IN3 (book=0x00 page=0x01 address=0x5C) [reset=0h]
      79. 14.2.79  ASIM_BUSKEEP (book=0x00 page=0x01 address=0x60) [reset=0h]
      80. 14.2.80  ASIM_MODE (book=0x00 page=0x01 address=0x61) [reset=8h]
      81. 14.2.81  ASIM_NUM_DEV (book=0x00 page=0x01 address=0x62) [reset=0h]
      82. 14.2.82  ASIM_FORMAT (book=0x00 page=0x01 address=0x63) [reset=10h]
      83. 14.2.83  ASIM_BDIV_CLK (book=0x00 page=0x01 address=0x64) [reset=1h]
      84. 14.2.84  ASIM_BDIV_RATIO (book=0x00 page=0x01 address=0x65) [reset=2h]
      85. 14.2.85  ASIM_WDIV_RATIO_1 (book=0x00 page=0x01 address=0x66) [reset=0h]
      86. 14.2.86  ASIM_WDIV_RATIO_2 (book=0x00 page=0x01 address=0x67) [reset=20h]
      87. 14.2.87  ASIM_BCLK (book=0x00 page=0x01 address=0x68) [reset=40h]
      88. 14.2.88  ASIM_WCLK (book=0x00 page=0x01 address=0x69) [reset=38h]
      89. 14.2.89  ASIM_DIN (book=0x00 page=0x01 address=0x6A) [reset=70h]
      90. 14.2.90  INT_GEN_1 (book=0x00 page=0x01 address=0x6C) [reset=0h]
      91. 14.2.91  INT_GEN_2 (book=0x00 page=0x01 address=0x6D) [reset=0h]
      92. 14.2.92  INT_GEN_3 (book=0x00 page=0x01 address=0x6E) [reset=0h]
      93. 14.2.93  INT_GEN_4 (book=0x00 page=0x01 address=0x6F) [reset=0h]
      94. 14.2.94  INT_GEN_5 (book=0x00 page=0x01 address=0x70) [reset=0h]
      95. 14.2.95  INT_GEN_6 (book=0x00 page=0x01 address=0x71) [reset=0h]
      96. 14.2.96  INT_IND_MODE (book=0x00 page=0x01 address=0x72) [reset=0h]
      97. 14.2.97  MAIN_CLK_PIN (book=0x00 page=0x01 address=0x73) [reset=Dh]
      98. 14.2.98  PLL_CLK_PIN (book=0x00 page=0x01 address=0x74) [reset=Dh]
      99. 14.2.99  CLKOUT_MUX (book=0x00 page=0x01 address=0x75) [reset=Dh]
      100. 14.2.100 CLKOUT_CDIV_RATIO (book=0x00 page=0x01 address=0x76) [reset=1h]
      101. 14.2.101 I2C_MISC (book=0x00 page=0x01 address=0x7C) [reset=0h]
      102. 14.2.102 DEVICE_ID (book=0x00 page=0x01 address=0x7D) [reset=12h]
      103. 14.2.103 PAGE (book=0x00 page=0x02 address=0x00) [reset=1h]
      104. 14.2.104 RAMP_CTRL (book=0x00 page=0x02 address=0x06) [reset=0h]
      105. 14.2.105 PROTECTION_CFG (book=0x00 page=0x02 address=0x09) [reset=3h]
  15. 15器件和文档支持
    1. 15.1 文档支持
    2. 15.2 社区资源
    3. 15.3 商标
    4. 15.4 静电放电警告
    5. 15.5 Glossary
  16. 16机械、封装和可订购信息
    1. 16.1 封装尺寸

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • YZ|42
订购信息

Power Supply Recommendations

Power Supplies

The TAS2557 requires four power supplies:

  • Boost Input (terminal: VBAT)
    • Voltage: 2.9 V to 5.5 V
    • Max Current: 5 A for ILIM = 3.0 A (default)
  • Analog Supply (terminal: AVDD)
    • Voltage: 1.65 V to 1.95 V
    • Max Current: 30 mA
  • Digital Supply (terminal: DVDD)
    • Voltage: 1.65 V to 1.95 V
    • Max Current: 50 mA
  • Digital I/O Supply (terminal: IOVDD)
    • Voltage: 1.62 V to 3.6 V
    • Max Current: 5 mA

The decoupling capacitors for the power supplies should be placed close to the device terminals. For VBAT, IOVDD, DVDD and AVDD, a small decoupling capacitor of 0.1 µF should be placed close to the device terminals. Refer to Figure 43 for the schematic.

Power Supply Sequencing

The following power sequence should be followed for power up and power down. If the recommended sequence is not followed there can be large current in device due to faults in level shifters and diodes becoming forward biased. The Tdelay between power supplies should be large enough for the power rails to settle.

TAS2557 power_sequencing.gif Figure 45. Power Supply Sequence for Power-Up and Power-Down

When the supplies have settled, the /RESET terminal can be set HIGH to operate the device. Additionally the /RESET pin can be tied to IOVDD and the internal DVDD POR will perform a reset of the device. After a hardware or software reset additional commands to the device should be delayed for 100uS to allow the OTP to load. The above sequence should be completed before any I2C operation.