ZHCSS30E february 2006 – october 2020 SN65LVDS301
PRODUCTION DATA
Figure 9-1 shows a possible implementation of a VGA display. The LVDS301 interfaces to the SN65LVDS302, which is the corresponding receiver device to deserialize the data and drive the display driver. The pixel clock rate of 22 MHz assumes ~10% blanking overhead and 60 Hz display refresh rate. The application assumes 24-bit color resolution. It is also shown, how the application processor provides a powerdown (reset) signal for both serializer and the display driver. The signal count over the FPC could be further decreased by using the standby option on the SN65LVDS302 and pulling RXEN high with a 30 kΩ resistor to VDD.