ZHCSS30E february   2006  – october 2020 SN65LVDS301

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings #GUID-B6F760D2-14EB-4E2D-91AA-4EF9E63722A7/SLLS6819275
    2. 6.2  Thermal Information
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Device Electrical Characteristics
    5. 6.5  Output Electrical Characteristics
    6. 6.6  Input Electrical Characteristics
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Characteristics
    9. 6.9  Device Power Dissipation
    10. 6.10 Typical characteristics
  8. 7 Parameter Measurement Information
    1.     19
      1. 7.1.1 Power Consumption Tests
        1. 7.1.1.1 Typical IC Power Consumption Test Pattern
        2. 7.1.1.2 22
      2. 7.1.2 Maximum Power Consumption Test Pattern
      3. 7.1.3 Output Skew Pulse Position & Jitter Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Swap Pin Functionality
      2. 8.3.2 Parity Bit Generation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serialization Modes
        1. 8.4.1.1 1-Channel Mode
        2. 8.4.1.2 2-Channel Mode
        3. 8.4.1.3 3-Channel Mode
      2. 8.4.2 Powerdown Modes
      3. 8.4.3 Shutdown Mode
      4. 8.4.4 Standby Mode
      5. 8.4.5 Active Modes
      6. 8.4.6 Acquire Mode (PLL approaches lock)
      7. 8.4.7 Transmit Mode
      8. 8.4.8 Status Detect and Operating Modes Flow diagram
  10. 9 Application information
    1. 9.1 Application Information
    2. 9.2 Preventing Increased Leakage Currents in Control Inputs
    3. 9.3 VGA Application
    4. 9.4 Dual LCD-Display Application
    5. 9.5 Typical Application Frequencies
      1. 9.5.1 Calculation Example: HVGA Display
  11. 10Power Supply Design Recommendation
    1. 10.1 Decoupling Recommendation
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 支持资源
    2. 12.2 Trademarks
    3. 12.3 静电放电警告
    4. 12.4 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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9.5.1 Calculation Example: HVGA Display

This example calculation shows a typical Half-VGA display with these parameters:

Display Resolution:480 x 320
GUID-7B742626-A62D-49BA-A80F-A9B5A6BDAE4B-low.gifFigure 9-3 HVGA Display Parameters
Frame Refresh Rate:58.4 Hz
Horizontal Visible Pixel:480 columns
Horizontal Front Porch:20 columns
Horizontal Sync:5 columns
Horizontal Back Porch:3 columns
Vertical Visible Pixel:320 lines
Vertical Front Porch:10 lines
Vertical Sync:5 lines
Vertical Back Porch:3 lines

Calculation of the total number of pixel and Blanking overhead:

Visible Area Pixel Count:480 × 320 = 153600 pixel
Total Frame Pixel Count:(480+20+5+3) × (320+10+5+3) = 171704 pixel
Blanking Overhead:(171704-153600) ÷ 153600 = 11.8 %

The application requires following serial-link parameters:

Pixel Clk Frequency:171704 × 58.4 Hz = 10.0 MHz
Serial Data Rate:1-channel mode: 10.0 MHz × 30 bit/channel = 300 Mbps
2-channel mode: 10.0 MHz × 15 bit/channel = 150 Mbps