ZHCSS30E february   2006  – october 2020 SN65LVDS301

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings #GUID-B6F760D2-14EB-4E2D-91AA-4EF9E63722A7/SLLS6819275
    2. 6.2  Thermal Information
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Device Electrical Characteristics
    5. 6.5  Output Electrical Characteristics
    6. 6.6  Input Electrical Characteristics
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Characteristics
    9. 6.9  Device Power Dissipation
    10. 6.10 Typical characteristics
  8. 7 Parameter Measurement Information
    1.     19
      1. 7.1.1 Power Consumption Tests
        1. 7.1.1.1 Typical IC Power Consumption Test Pattern
        2. 7.1.1.2 22
      2. 7.1.2 Maximum Power Consumption Test Pattern
      3. 7.1.3 Output Skew Pulse Position & Jitter Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Swap Pin Functionality
      2. 8.3.2 Parity Bit Generation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serialization Modes
        1. 8.4.1.1 1-Channel Mode
        2. 8.4.1.2 2-Channel Mode
        3. 8.4.1.3 3-Channel Mode
      2. 8.4.2 Powerdown Modes
      3. 8.4.3 Shutdown Mode
      4. 8.4.4 Standby Mode
      5. 8.4.5 Active Modes
      6. 8.4.6 Acquire Mode (PLL approaches lock)
      7. 8.4.7 Transmit Mode
      8. 8.4.8 Status Detect and Operating Modes Flow diagram
  10. 9 Application information
    1. 9.1 Application Information
    2. 9.2 Preventing Increased Leakage Currents in Control Inputs
    3. 9.3 VGA Application
    4. 9.4 Dual LCD-Display Application
    5. 9.5 Typical Application Frequencies
      1. 9.5.1 Calculation Example: HVGA Display
  11. 10Power Supply Design Recommendation
    1. 10.1 Decoupling Recommendation
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 支持资源
    2. 12.2 Trademarks
    3. 12.3 静电放电警告
    4. 12.4 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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6.3 Recommended Operating Conditions(1)

MINNOMMAXUNIT
VDD
VDDPLLA
VDDPLLD
VDDLVDS		Supply voltages1.651.81.95V
VDDn(PP)Supply voltage noise magnitude (all supplies)Test set-up see Figure 7-5mV
f(PCLK) ≤ 50 MHz; f(noise) = 1 Hz to 2 GHz100
f(PCLK) > 50 MHz; f(noise) = 1 Hz to 1 MHz100
f(PCLK) > 50 MHz; f(noise) > 1 MHz40
fPCLKPixel clock frequency1-Channel transmit mode, see Figure 8-4415MHz
2-Channel transmit mode, see Figure 8-5830
3-Channel transmit mode, see Figure 8-62065
Frequency threshold Standby mode to active mode(2), see Figure 7-90.53
tH x fPCLKPCLK input duty cycle0.330.67
TAOperating free-air temperature–4085°C
tjit(per)PCLKPCLK RMS period jitter(3)Measured on PCLK input5ps-rms
tjit(TJ)PCLKPCLK total jitter0.05/fPCLKs
tjit(CC)PCLKPCLK peak
cycle-to-cycle jitter(4)		0.02/fPCLKs
PCLK, R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, LS[1:0], CPOL, TXEN, SWAP
VIHHigh-level input voltage0.7×VDDVDDV
VILLow-level input voltage0.3×VDDV
tDSData set up time prior to PCLK transition
f (PCLK) = 65 MHz; see Figure 7-12.0ns
tDHData hold time after PCLK transition2.0ns
(1) Unused single-ended inputs must be held high or low to prevent them from floating.
(2) PCLK input frequencies lower than 500 kHz force the SN65LVDS301into standby mode. Input frequencies between 500 kHz and 3 MHz may or may not activate the SN65LVDS301. Input frequencies beyond 3 MHz activate the SN65LVDS301.
(3) Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles.
(4) Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles; over a random sample of 1,000 adjacent cycle pairs.