ZHCSS30E february   2006  – october 2020 SN65LVDS301

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings #GUID-B6F760D2-14EB-4E2D-91AA-4EF9E63722A7/SLLS6819275
    2. 6.2  Thermal Information
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Device Electrical Characteristics
    5. 6.5  Output Electrical Characteristics
    6. 6.6  Input Electrical Characteristics
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Characteristics
    9. 6.9  Device Power Dissipation
    10. 6.10 Typical characteristics
  8. 7 Parameter Measurement Information
    1.     19
      1. 7.1.1 Power Consumption Tests
        1. 7.1.1.1 Typical IC Power Consumption Test Pattern
        2. 7.1.1.2 22
      2. 7.1.2 Maximum Power Consumption Test Pattern
      3. 7.1.3 Output Skew Pulse Position & Jitter Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Swap Pin Functionality
      2. 8.3.2 Parity Bit Generation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serialization Modes
        1. 8.4.1.1 1-Channel Mode
        2. 8.4.1.2 2-Channel Mode
        3. 8.4.1.3 3-Channel Mode
      2. 8.4.2 Powerdown Modes
      3. 8.4.3 Shutdown Mode
      4. 8.4.4 Standby Mode
      5. 8.4.5 Active Modes
      6. 8.4.6 Acquire Mode (PLL approaches lock)
      7. 8.4.7 Transmit Mode
      8. 8.4.8 Status Detect and Operating Modes Flow diagram
  10. 9 Application information
    1. 9.1 Application Information
    2. 9.2 Preventing Increased Leakage Currents in Control Inputs
    3. 9.3 VGA Application
    4. 9.4 Dual LCD-Display Application
    5. 9.5 Typical Application Frequencies
      1. 9.5.1 Calculation Example: HVGA Display
  11. 10Power Supply Design Recommendation
    1. 10.1 Decoupling Recommendation
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 支持资源
    2. 12.2 Trademarks
    3. 12.3 静电放电警告
    4. 12.4 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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8.4.8 Status Detect and Operating Modes Flow diagram

The SN65LVDS301 switches between the power saving and active modes in the following way:

GUID-A31541B2-0895-4A4B-A9D2-6CF86398AC97-low.gifFigure 8-7 Status Detect and Operating Modes Flow Diagram
Table 8-3 Status Detect and Operating Modes Descriptions
ModeCharacteristicsConditions
Shutdown ModeLeast amount of power consumption(1) (most circuitry turned off); All outputs are high-impedanceTXEN is low(1) (2)
Standby ModeLow power consumption (only clock activity circuit active; PLL is disabled to conserve power); All outputs are high-impedanceTXEN is high; PCLK input signal is missing or inactive(2)
Acquire ModePLL tries to achieve lock; All outputs are high-impedanceTXEN is high; PCLK input monitor detected input activity
Transmit ModeData transfer (normal operation); Transmitter serializes data and transmits data on serial output; unused outputs remain high-impedanceTXEN is high and PLL is locked to incoming clock
(1) In Shutdown Mode, all SN65LVDS301 internal switching circuits (e.g., PLL, serializer, etc.) are turned off to minimize power consumption. The input stage of any input pin remains active.
(2) Leaving inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. All inputs must be tied to a valid logic level VIL or VIH during Shutdown or Standby Mode.
Table 8-4 Operating Mode Transitions
MODE TRANSITIONUSE CASETRANSITION SPECIFICS
Shutdown → StandbyDrive TXEN high to enable transmitter1.TXEN high > 10 μs
2.Transmitter enters standby mode
a. All outputs are high-impedance
b. Transmitter turns on clock input monitor
Standby → AcquireTransmitter activity detected1.PCLK input monitor detects clock input activity;
2.Outputs remain high-impedance;
3.PLL circuit is enabled
Acquire → TransmitLink is ready to transfer data1.PLL is active and approaches lock
2.PLL achieved lock within 2 ms
3.Parallel Data input latches into shift register
4.CLK output turns on
5.selected Data outputs turn on and send out first serial data bit
Transmit → StandbyRequest Transmitter to enter Standby mode by stopping PCLK1.PCLK Input monitor detects missing PCLK
2.Transmitter indicates standby, putting all outputs into high-impedance;
3.PLL shuts down;
4.PCLK activity input monitor remains active
Transmit/Standby → ShutdownTurn off Transmitter1.TXEN pulled low for longer than 10us
2.Transmitter indicates standby, putting output CLK+ and CLK– into high-impedance state;
3.Transmitter puts all other outputs into high-impedance state
4.Most IC circuitry is shut down for least power consumption