ZHCSS30E february   2006  – october 2020 SN65LVDS301

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings #GUID-B6F760D2-14EB-4E2D-91AA-4EF9E63722A7/SLLS6819275
    2. 6.2  Thermal Information
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Device Electrical Characteristics
    5. 6.5  Output Electrical Characteristics
    6. 6.6  Input Electrical Characteristics
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Characteristics
    9. 6.9  Device Power Dissipation
    10. 6.10 Typical characteristics
  8. 7 Parameter Measurement Information
    1.     19
      1. 7.1.1 Power Consumption Tests
        1. 7.1.1.1 Typical IC Power Consumption Test Pattern
        2. 7.1.1.2 22
      2. 7.1.2 Maximum Power Consumption Test Pattern
      3. 7.1.3 Output Skew Pulse Position & Jitter Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Swap Pin Functionality
      2. 8.3.2 Parity Bit Generation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serialization Modes
        1. 8.4.1.1 1-Channel Mode
        2. 8.4.1.2 2-Channel Mode
        3. 8.4.1.3 3-Channel Mode
      2. 8.4.2 Powerdown Modes
      3. 8.4.3 Shutdown Mode
      4. 8.4.4 Standby Mode
      5. 8.4.5 Active Modes
      6. 8.4.6 Acquire Mode (PLL approaches lock)
      7. 8.4.7 Transmit Mode
      8. 8.4.8 Status Detect and Operating Modes Flow diagram
  10. 9 Application information
    1. 9.1 Application Information
    2. 9.2 Preventing Increased Leakage Currents in Control Inputs
    3. 9.3 VGA Application
    4. 9.4 Dual LCD-Display Application
    5. 9.5 Typical Application Frequencies
      1. 9.5.1 Calculation Example: HVGA Display
  11. 10Power Supply Design Recommendation
    1. 10.1 Decoupling Recommendation
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 支持资源
    2. 12.2 Trademarks
    3. 12.3 静电放电警告
    4. 12.4 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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6.7 Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
tr20%-to-80% differential output signal rise timeSee Figure 7-2 and Figure 7-3250500ps
tf20%-to-80% differential output signal fall timeSee Figure 7-2 and Figure 7-3250500
fBWPLL bandwidth (3dB cutoff frequency)Tested from PCLK input to CLK output, See Figure 6-1 (3)fPCLK = 22 MHz0.082 × fPCLKMHz
fPCLK = 65 MHz0.07 × fPCLK
tpd(L)Propagation delay time, input to serial output (data latency Figure 7-4)TXEN at VDD, VIH=VDD, VIL=GND, RL=100 Ω1-channel mode0.8/fPCLK1/fPCLK1.2/fPCLKs
2-channel mode1.0/fPCLK1.21/fPCLK1.5/fPCLK
3-channel mode1.1/fPCLK1.31/fPCLK1.6/fPCLK
tH × fCLK0Output CLK duty cycle1-channel and 3-channel mode0.450.500.55
2-channel mode0.490.530.58
tGSTXEN Glitch suppression pulse width(2)VIH=VDD, VIL=GND, TXEN toggles between VIL and VIH, see Figure 7-7 and Figure 7-83.810μs
tpwrupEnable time from power down (↑TXEN)Time from TXEN pulled high to CLK and Dx outputs enabled and transmit valid data; see Figure 7-80.242ms
tpwrdnDisable time from active mode (↓TXEN)TXEN is pulled low during transmit mode; time measurement until output is disabled and PLL is Shutdown; see Figure 7-80.511μs
twakupEnable time from Standby (↕PCLK)TXEN at VDD; device in standby; time measurement from PCLK starts switching to CLK and Dx outputs enabled and transmit valid data; see Figure 7-80.232ms
tsleepDisable time from Active mode (PCLK stopping)TXEN at VDD; device is transmitting; time measurement from PCLK input signal stops until CLK + Dx outputs are disabled and PLL is disabled; see Figure 7-80.4100μs
(1) All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
(2) The TXEN input incorporates glitch-suppression circuitry to disregard short input pulses. tGS is the duration of either a high-to-low or low-to-high transition that is suppressed.
(3) The Maximum Limit is based on statistical analysis of the device performance over process, voltage, and temp ranges. This parameter is functionality tested only on Automatic Test Equipment (ATE).
GUID-481FC2C3-083D-42E4-91F6-D51480BD62C2-low.gifFigure 6-1 LVDS301 PLL Bandwidth (also showing the LVDS302 PLL bandwidth)