ZHCSS30E february   2006  – october 2020 SN65LVDS301

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings #GUID-B6F760D2-14EB-4E2D-91AA-4EF9E63722A7/SLLS6819275
    2. 6.2  Thermal Information
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Device Electrical Characteristics
    5. 6.5  Output Electrical Characteristics
    6. 6.6  Input Electrical Characteristics
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Characteristics
    9. 6.9  Device Power Dissipation
    10. 6.10 Typical characteristics
  8. 7 Parameter Measurement Information
    1.     19
      1. 7.1.1 Power Consumption Tests
        1. 7.1.1.1 Typical IC Power Consumption Test Pattern
        2. 7.1.1.2 22
      2. 7.1.2 Maximum Power Consumption Test Pattern
      3. 7.1.3 Output Skew Pulse Position & Jitter Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Swap Pin Functionality
      2. 8.3.2 Parity Bit Generation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serialization Modes
        1. 8.4.1.1 1-Channel Mode
        2. 8.4.1.2 2-Channel Mode
        3. 8.4.1.3 3-Channel Mode
      2. 8.4.2 Powerdown Modes
      3. 8.4.3 Shutdown Mode
      4. 8.4.4 Standby Mode
      5. 8.4.5 Active Modes
      6. 8.4.6 Acquire Mode (PLL approaches lock)
      7. 8.4.7 Transmit Mode
      8. 8.4.8 Status Detect and Operating Modes Flow diagram
  10. 9 Application information
    1. 9.1 Application Information
    2. 9.2 Preventing Increased Leakage Currents in Control Inputs
    3. 9.3 VGA Application
    4. 9.4 Dual LCD-Display Application
    5. 9.5 Typical Application Frequencies
      1. 9.5.1 Calculation Example: HVGA Display
  11. 10Power Supply Design Recommendation
    1. 10.1 Decoupling Recommendation
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 支持资源
    2. 12.2 Trademarks
    3. 12.3 静电放电警告
    4. 12.4 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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6.4 Device Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
IDD 1ChM VDD =VDDPLLA=VDDPLLD=VDDLVDS, RL(CLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V, TXEN at VDD,
alternating 1010 serial bit pattern		 fPCLK = 4 MHz 9.0 11.4 mA
fPCLK = 6 MHz 10.6 12.6
fPCLK = 15 MHz 16 18.8
VDD =VDDPLLA=VDDPLLD=VDDLVDS, RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V, TXEN at VDD,
typical power test pattern (see Table 7-2)		 fPCLK = 4 MHz 8.0 mA
fPCLK = 6 MHz 8.9
fPCLK = 15 MHz 14.0
2ChM VDD =VDDPLLA=VDDPLLD=VDDLVDS, RL(CLK)=RL(Dx)=100 Ω, VIH=VDD, VIL=0 V, TXEN at VDD,
alternating 1010 serial bit pattern;		 fPCLK = 8 MHz 13.7 15.9 mA
fPCLK = 22 MHz 18.4 22.0
fPCLK = 30 MHz 21.4 25.8
VDD =VDDPLLA=VDDPLLD=VDDLVDS, RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V, TXEN at VDD,
typical power test pattern (see Table 7-3)		 fPCLK = 8 MHz 11.5 mA
fPCLK = 22 MHz 16.0
fPCLK = 30 MHz 19.1
3ChM VDD =VDDPLLA=VDDPLLD=VDDLVDS, RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V, TXEN at VDD,
alternating 1010 serial bit pattern		 fPCLK = 20 MHz 20.0 22.5 mA
fPCLK = 65 MHz 29.1 36.8
VDD =VDDPLLA=VDDPLLD=VDDLVDS, RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V, TXEN at VDD,
typical power test pattern (see Table 7-4)		 fPCLK = 20 MHz 15.9 mA
fPCLK = 65 MHz 24.7
Standby Mode VDD = VDDPLLA = VDDPLLD = VDDLVDS, RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V, all inputs held static high or static low 0.61 10 μA
Shutdown Mode 0.55 10 μA
(1) All typical values are at 25°C and with 1.8 V supply unless otherwise noted.