ZHCSS30E february 2006 – october 2020 SN65LVDS301
PRODUCTION DATA
The SN65LVDS301 supports pixel clock frequencies from 4 MHz to 65 MHz over 1, 2, or 3 data lanes. Table 9-1 provides a few typical display resolution examples and shows the number of data lanes necessary to connect the LVDS301 with the display. The blanking overhead is assumed to be 20%. Often, blanking overhead is smaller, resulting in a lower data rate. Furthermore, the examples in the table assumes a display frame refresh rate of 60 Hz or 90 Hz. The actual refresh rate may differ depending on the application-processor clock implementation.
| Display Screen Resolution | Visible Pixel Count | Blanking Overhead | Display Refresh Rate | Pixel Clock Frequency [MHz] | Serial Data Rate Per Lane | ||
|---|---|---|---|---|---|---|---|
| 1-ChM | 2-ChM | 3-ChM | |||||
| 176x220 (QCIF+) | 38,720 | 20% | 90 Hz | 4.2 MHz | 125 Mbps | ||
| 240x320 (QVGA) | 76,800 | 60 Hz | 5.5 MHz | 166 Mbps | |||
| 640x200 | 128,000 | 9.2 MHz | 276 Mbps | 138 Mbps | |||
| 352x416 (CIF+) | 146,432 | 10.5 MHz | 316 Mbps | 158 Mbps | |||
| 352x440 | 154,880 | 11.2 MHz | 335 Mbps | 167 Mbps | |||
| 320x480 (HVGA) | 153,600 | 11.1 MHz | 332 Mbps | 166 Mbps | |||
| 800x250 | 200,000 | 14.4 MHz | 432 Mbps | 216 Mbps | |||
| 640x320 | 204,800 | 14.7 MHz | 442 Mbps | 221 Mbps | |||
| 640x480 (VGA) | 307,200 | 22.1 MHz | 332 Mbps | 221 Mbps | |||
| 1024x320 | 327,680 | 23.6 MHz | 354 Mbps | 236 Mbps | |||
| 854x480 (WVGA) | 409,920 | 29.5 MHz | 443 Mbps | 295 Mbps | |||
| 800x600 (SVGA) | 480,000 | 34.6 MHz | 346 Mbps | ||||
| 1024x768 (XGA) | 786,432 | 56.6 MHz | 566 Mbps | ||||