ZHCSGM4C August   2017  – October 2023 OPA838

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = 5 V
    6. 7.6 Electrical Characteristics: VS = 3 V
    7. 7.7 Typical Characteristics: VS = 5 V
    8. 7.8 Typical Characteristics: VS = 3 V
    9. 7.9 Typical Characteristics: Over Supply Range
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Common-Mode Voltage Range
      2. 8.3.2 Output Voltage Range
      3. 8.3.3 Power-Down Operation
      4. 8.3.4 Trade-Offs in Selecting The Feedback Resistor Value
      5. 8.3.5 Driving Capacitive Loads
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
      2. 8.4.2 Single-Supply Operation (2.7 V to 5.4 V)
      3. 8.4.3 Power Shutdown Operation
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Noninverting Amplifier
      2. 9.1.2 Inverting Amplifier
      3. 9.1.3 Output DC Error Calculations
      4. 9.1.4 Output Noise Calculations
    2. 9.2 Typical Applications
      1. 9.2.1 High-Gain Differential I/O Designs
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Transimpedance Amplifier
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 TINA-TI™ Simulation Model Features
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12.   Mechanical, Packaging, and Orderable Information

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9.2.2.2 Detailed Design Procedure

The primary design requirement is to set the achievable transimpedance gain and compensate the operational amplifier with CF for the desired response shape. A detailed transimpedance design methodology is available in Transimpedance Considerations for High-Speed Amplifiers. With a source capacitance set and the amplifier selected to provide a particular gain bandwidth product, the achievable transimpedance gain and resulting Butterworth bandwidth are tightly coupled as Equation 5 illustrates. Use Equation 6 to solve for a maximum RF value. When the RF is selected, the feedback pole is set by Equation 7 to be at 0.707 of the characteristic frequency. At that compensation point, the closed-loop bandwidth is that characteristic frequency with a Butterworth response.

  • With the 100-pF source capacitance, 300-MHz gain bandwidth product, and the 2.2-MHz closed-loop bandwidth target in the transimpedance stage, solve Equation 6 for a maximum gain of 100 kΩ.
  • Set the feedback pole at 0.707 times that 2.2-MHz Butterworth bandwidth. This sets the target 1 / (2π × R F × CF) = 1.55 MHz. Solving for CF sets the target to 1 pF
  • If dc precision is desired, add a 100-kΩ resistor to ground on the noninverting input. If DC precision is not required, ground the noninverting input
  • Add a resistor noise filtering capacitor in parallel with the 100-kΩ resistor.
  • Add a small series resistor isolating this capacitor from the noninverting input.
  • Select a final filter capacitor for the load. (In this example, a value of 2.2 nF is used as a typical SAR input capacitor.)
  • Add a series resistor to the final filter capacitor to form a 1-MHz pole. In this example, that is 73.2 Ω.
  • Confirm this resistor is greater than the minimum recommended value illustrated in Figure 7-49.
Equation 5. GUID-C4DE543D-0E91-4ADE-8A97-EB58458A426B-low.gif
Equation 6. GUID-D67E4BC2-F8D6-42CE-86FA-D2F269B10638-low.gif
Equation 7. GUID-ABEB04AA-50BA-41BF-B87A-7D6984A0600C-low.gif

Implementing this design and simulating the performance using the TINA model for the response to the output pin and to the final capacitive load shows the expected results of Figure 9-8. Here, the exact 2.2-MHz flat Butterworth response to the output pin is shown with the final single pole rolloff at 1 MHz at the final 2.2-nF capacitor.