ZHCSGM4C August   2017  – October 2023 OPA838

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = 5 V
    6. 7.6 Electrical Characteristics: VS = 3 V
    7. 7.7 Typical Characteristics: VS = 5 V
    8. 7.8 Typical Characteristics: VS = 3 V
    9. 7.9 Typical Characteristics: Over Supply Range
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Common-Mode Voltage Range
      2. 8.3.2 Output Voltage Range
      3. 8.3.3 Power-Down Operation
      4. 8.3.4 Trade-Offs in Selecting The Feedback Resistor Value
      5. 8.3.5 Driving Capacitive Loads
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
      2. 8.4.2 Single-Supply Operation (2.7 V to 5.4 V)
      3. 8.4.3 Power Shutdown Operation
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Noninverting Amplifier
      2. 9.1.2 Inverting Amplifier
      3. 9.1.3 Output DC Error Calculations
      4. 9.1.4 Output Noise Calculations
    2. 9.2 Typical Applications
      1. 9.2.1 High-Gain Differential I/O Designs
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Transimpedance Amplifier
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 TINA-TI™ Simulation Model Features
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12.   Mechanical, Packaging, and Orderable Information

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8.3.5 Driving Capacitive Loads

The OPA838 can drive small capacitive loads directly without oscillation (less than 6@pF). When driving capacitive loads greater than 6 pF, Figure 7-49 illustrates the recommended ROUT vs capacitor load parametric on gains. At higher gains, the amplifier starts with greater phase margin into a resistive load and can operate with lower ROUT for a given capacitive load. Without ROUT, output capacitance interacts with the output impedance of the amplifier, which causes phase shift in the loop gain of the amplifier that reduces the phase margin. This causes peaking in the frequency response with overshoot and ringing in the pulse response. Figure 7-49 targets a 30° phase margin for the OPA838. A 30° phase margin produces a 5.7‑dB peaking in the frequency response at the amplifier output pin that is rolled off by the output RC pole; see Figure 8-7. This peaking can cause clipping for large signals driving a capacitive load. Increasing the ROUT value can reduce the peaking at the cost of a more band-limited overall response.

GUID-AB89246B-26FC-4FF1-9C9E-01F308838D77-low.gif Figure 8-6 ROUT versus CL Test Circuit
GUID-3CC7C320-B900-4C86-AA4E-4518022AC5DE-low.gif Figure 8-7 Frequency Response to Output Pin and Capacitive Load