ZHCSGM4C August   2017  – October 2023 OPA838

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = 5 V
    6. 7.6 Electrical Characteristics: VS = 3 V
    7. 7.7 Typical Characteristics: VS = 5 V
    8. 7.8 Typical Characteristics: VS = 3 V
    9. 7.9 Typical Characteristics: Over Supply Range
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Common-Mode Voltage Range
      2. 8.3.2 Output Voltage Range
      3. 8.3.3 Power-Down Operation
      4. 8.3.4 Trade-Offs in Selecting The Feedback Resistor Value
      5. 8.3.5 Driving Capacitive Loads
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
      2. 8.4.2 Single-Supply Operation (2.7 V to 5.4 V)
      3. 8.4.3 Power Shutdown Operation
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Noninverting Amplifier
      2. 9.1.2 Inverting Amplifier
      3. 9.1.3 Output DC Error Calculations
      4. 9.1.4 Output Noise Calculations
    2. 9.2 Typical Applications
      1. 9.2.1 High-Gain Differential I/O Designs
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Transimpedance Amplifier
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 TINA-TI™ Simulation Model Features
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12.   Mechanical, Packaging, and Orderable Information

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9.2.1.2 Detailed Design Procedure

  • Set the total R G value near the high gain values using Table 9-1. This 178-Ω total must be split for a center tap to increase the common-mode noise gain, as shown by the 88.7-Ω value in Figure 9-4.
  • Set RF using a standard value near the calculated from solving Equation 1 using half of the total RG value.
  • Simulate the common-mode noise with different elements on the RG center tap as shown in Figure 9-5. Decide which is most appropriate to the application.

The common-mode loop instability without the RG center tap is not often apparent in the closed-loop differential simulations. The common-mode loop instability without the RG center tap can often be detected in a common-mode output-noise simulation as Figure 9-5 shows. Grounding the inputs Figure 9-4 and running an output-noise simulation for the common-mode tap point in Figure 9-3 shows a peaking in the noise at high frequency. This peaking indicates low-phase margin for the common-mode loop. Figure 9-5 shows this peaking in the lowest noise curve, with two options for improving phase margin. The first option used in Figure 9-4 is a capacitor to ground set to increase the common-mode noise gain only at higher frequencies. This increase can be seen by the peaking in the common-mode noise of Figure 9-5. Another alternative is to provide a dc voltage reference on the RG center tap. This method raises the common-mode noise gain from dc and beyond. Neither of these latter two options show any evidence of low phase-margin peaking. These two options do increase the output common-mode noise significantly at lower frequencies. Typically, an increase in output common-mode noise is more acceptable than low-phase margin because the next stage (FDA, ADC, differential to single stage) rejects common-mode noise.

Using the 10-nF center tap capacitor, Figure 9-6 shows the differential I/O small-signal response showing the expected 300 MHz / 41 ≈ 7.3 MHz closed-loop bandwidth. The capacitor to ground between the RG elements does not impact the differential frequency response.