ZHCSGM4C August   2017  – October 2023 OPA838

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = 5 V
    6. 7.6 Electrical Characteristics: VS = 3 V
    7. 7.7 Typical Characteristics: VS = 5 V
    8. 7.8 Typical Characteristics: VS = 3 V
    9. 7.9 Typical Characteristics: Over Supply Range
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Common-Mode Voltage Range
      2. 8.3.2 Output Voltage Range
      3. 8.3.3 Power-Down Operation
      4. 8.3.4 Trade-Offs in Selecting The Feedback Resistor Value
      5. 8.3.5 Driving Capacitive Loads
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
      2. 8.4.2 Single-Supply Operation (2.7 V to 5.4 V)
      3. 8.4.3 Power Shutdown Operation
  10. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Noninverting Amplifier
      2. 9.1.2 Inverting Amplifier
      3. 9.1.3 Output DC Error Calculations
      4. 9.1.4 Output Noise Calculations
    2. 9.2 Typical Applications
      1. 9.2.1 High-Gain Differential I/O Designs
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Transimpedance Amplifier
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 TINA-TI™ Simulation Model Features
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12.   Mechanical, Packaging, and Orderable Information

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Inverting Amplifier

The OPA838 can be used as an inverting amplifier with signal input to the inverting input (VIN–) through the gain-setting resistor (RG.) Figure 8-2 illustrates a basic block diagram of the circuit.

If VIN = VREF + VSIG, and the noninverting input is dc biased to VREF, the output of the amplifier is calculated according to Equation 2:

Equation 2. GUID-3DBDEF61-9260-4CF2-9E15-5B7AA22D2604-low.gif

The signal gain of the circuit GUID-BB7E808A-291A-4D8A-B0A0-0187BFC92305-low.gif and VREF provides a reference point around which the input and output signals swing. For bipolar-supply operation, VREF is often GND. The output signal is 180° out-of-phase with the input signal in the pass band of the application. Figure 9-2 illustrates the 50-Ω input matched configuration used for the inverting characterization plots. In this case, an added termination resistor is placed in parallel with the input RG resistor to provide an impedance match to 50-Ω test equipment. Table 9-2 lists the suggested values for RF, RG, and RT for inverting gains from –6 V/V to –20 V/V.

GUID-EC7FC76F-F039-4A8D-98CA-14A3AA8632B1-low.gif Figure 9-2 Inverting With Input Impedance Matching
Table 9-2 Inverting Recommended Resistor Values
AVERAGE RF (Ω) RG (Ω) EXACT RT STANDARD RT INPUT ZI ACTUAL (V/V) GAIN (dB)
–6 1180 196 67.1 66.5 49.7 –6.02 15.59
–7 1370 196 67.1 66.5 49.7 –6.99 16.89
–8 1540 191 67.7 68.1 50.2 –8.06 18.13
–9 1690 187 68.2 68.1 49.9 –9.04 19.12
–10 1870 187 68.2 68.1 49.9 –10 20
–11 2050 187 68.2 68.1 49.9 –10.96 20.80
–12 2210 182 68.9 68.1 49.6 –12.14 21.69
–13 2370 182 68.9 68.1 49.6 –13.02 22.29
–14 2550 182 68.9 68.1 49.6 –14.01 22.93
–15 2740 182 68.9 68.1 49.6 –15.05 23.55
–16 2870 178 69.5 69.8 50.1 –16.12 24.15
–17 3090 182 68.9 69.8 50.5 –16.98 24.6
–18 3240 178 69.5 69.8 50.1 –18.20 25.2
–19 3400 178 69.5 69.8 50.1 –19.10 25.62
–20 3570 178 69.5 69.8 50.1 –20.06 26.04