ZHCSGM4C August   2017  – October 2023 OPA838

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = 5 V
    6. 7.6 Electrical Characteristics: VS = 3 V
    7. 7.7 Typical Characteristics: VS = 5 V
    8. 7.8 Typical Characteristics: VS = 3 V
    9. 7.9 Typical Characteristics: Over Supply Range
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Common-Mode Voltage Range
      2. 8.3.2 Output Voltage Range
      3. 8.3.3 Power-Down Operation
      4. 8.3.4 Trade-Offs in Selecting The Feedback Resistor Value
      5. 8.3.5 Driving Capacitive Loads
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
      2. 8.4.2 Single-Supply Operation (2.7 V to 5.4 V)
      3. 8.4.3 Power Shutdown Operation
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Noninverting Amplifier
      2. 9.1.2 Inverting Amplifier
      3. 9.1.3 Output DC Error Calculations
      4. 9.1.4 Output Noise Calculations
    2. 9.2 Typical Applications
      1. 9.2.1 High-Gain Differential I/O Designs
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Transimpedance Amplifier
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 TINA-TI™ Simulation Model Features
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12.   Mechanical, Packaging, and Orderable Information

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7.9 Typical Characteristics: Over Supply Range

at PD = VS+ and TA = 25°C (unless otherwise noted)

GUID-0017245E-EC29-4E3B-B92E-ED66E0BD8667-low.gif
No load, simulation
Figure 7-37 Open-Loop Gain and Phase
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Figure 7-39 Input Spot Noise Density
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Simulated results
Figure 7-41 PSRR and CMRR
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600 units at each supply voltage
Figure 7-43 Input Offset Voltage Distribution
GUID-DF8F312A-AE3B-46DB-974A-AB5995F3F550-low.gif
51 units at 5-V and 3-V supply
Figure 7-45 Input Offset Voltage vs Temperature
GUID-7E4EDFC5-5D66-4667-A368-109B58CAC510-low.gif
51 units at each supply
Figure 7-47 Input Offset Voltage Drift Distribution
GUID-DC481112-6E30-4DDA-B815-0026E877E304-low.gif
See Figure 8-6 and Table 9-1
small signal, targeting 30° phase margin
Figure 7-49 Output Resistor vs CLOAD
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Figure 7-51 Turn-On Time to Sinusoidal Input
GUID-1749CE88-499E-4599-BEFC-0C00C21F445D-low.gif
Single-supply, DC input to produce midscale output (simulation)
Figure 7-53 Gain of 6-V/V Turn-On Time to Final DC Value at Midscale
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Figure 7-55 Output Voltage Swing vs Load Resistor
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Figure 7-57 Quiescent Current vs Temperature
GUID-8B9F8913-C258-425E-8D39-FC528EE3D986-low.gif
5 units, 3-V and 5-V supplies
Figure 7-59 Input Offset Voltage vs Input Common-Mode Voltage
GUID-CC0C24DD-DE8E-45A2-A4EB-E28FB0B07DA8-low.gif
See Figure 9-1 and Table 9-1 (simulation)
Figure 7-38 Closed-Loop Output Impedance
GUID-4EAA3F82-3E93-411E-B3BB-C92EC9DC1DBC-low.gif
Input referred
Figure 7-40 Low-Frequency Voltage Noise
GUID-B3341BA4-DE26-44F5-AED6-D4020EC65481-low.gif
Measured, AV = 6 V/V, 100-Ω load
Figure 7-42 Disabled Isolation Noninverting Input to Output
GUID-61A696D1-59A0-48D4-908A-F071B148E395-low.gif
600 units at each supply voltage
Figure 7-44 Input Offset Current Distribution
GUID-47381C4A-6846-4B22-9029-DA66B8AB22AD-low.gif
51 units at 5-V and 3-V supply
Figure 7-46 Input Offset Current vs Temperature
GUID-E77EC3D9-2551-417B-BCA9-B99679B599AE-low.gif
51 units at each supply
Figure 7-48 Input Offset Current Drift Distribution
GUID-1200CF8F-EBE3-4DBC-BA67-0ECEB6B48B66-low.gif
See Figure 8-6 and Table 9-1
2-kΩ parallel load to C LOAD
Figure 7-50 Small-Signal Response Shapes vs CLOAD With Recommended ROUT
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Figure 7-52 Turn-Off Time to Sinusoidal Input
GUID-3F0B5AFB-D97E-4EC0-A7DC-2E12F09E2D75-low.gif
Single-supply, DC input to produce midscale output (simulation)
Figure 7-54 Gain of 10-V/V Turn-On Time to Final DC Value at Midscale
GUID-58FA0708-3A61-4319-BF46-F031363B2C9F-low.gif
 
Figure 7-56 Output Saturation Voltage vs Load Current
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Figure 7-58 Supply Current vs Power-Down Voltage:
Turn On Higher Than Turn Off
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Measured single device
Figure 7-60 Input Bias and Offset Current vs VICM