ZHCSGM4C August   2017  – October 2023 OPA838

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = 5 V
    6. 7.6 Electrical Characteristics: VS = 3 V
    7. 7.7 Typical Characteristics: VS = 5 V
    8. 7.8 Typical Characteristics: VS = 3 V
    9. 7.9 Typical Characteristics: Over Supply Range
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Common-Mode Voltage Range
      2. 8.3.2 Output Voltage Range
      3. 8.3.3 Power-Down Operation
      4. 8.3.4 Trade-Offs in Selecting The Feedback Resistor Value
      5. 8.3.5 Driving Capacitive Loads
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
      2. 8.4.2 Single-Supply Operation (2.7 V to 5.4 V)
      3. 8.4.3 Power Shutdown Operation
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Noninverting Amplifier
      2. 9.1.2 Inverting Amplifier
      3. 9.1.3 Output DC Error Calculations
      4. 9.1.4 Output Noise Calculations
    2. 9.2 Typical Applications
      1. 9.2.1 High-Gain Differential I/O Designs
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Transimpedance Amplifier
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 TINA-TI™ Simulation Model Features
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12.   Mechanical, Packaging, and Orderable Information

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8.3.4 Trade-Offs in Selecting The Feedback Resistor Value

The OPA838 is specified using a 1-kΩ feedback resistor with a 200-Ω gain resistor to ground in a noninverting gain of 6 V/V configuration. These values give a good compromise, keeping the noise contribution of the resistors well below that of the amplifier noise terms and minimal power in the feedback network as the output voltage swing creates load current back into the feedback network. Decreasing these values improves the noise at the cost of more power dissipated in the feedback network. Low values increase the harmonic distortion as the feedback load decreases. Increasing the RF value at a particular gain increases the output noise contribution of those resistors possibly becoming dominant. As the feedback resistor values continue to increase (and the RG at a fixed target gain), there is a loss of phase margin as the impedance that drives the inverting input capacitance brings in an added loop pole at lower frequencies. Figure 8-3 shows this at a gain of 6 V/V with increasing RF values. This noninverting test shows more peaking as the RF values increase due to the 1-pF
common-mode input capacitance at the inverting input. The TINA simulation model gives excellent prediction of these effects.

GUID-950FC328-25C6-4DD7-BEFD-B59960854F1F-low.gifFigure 8-3 Frequency Response With Various Feedback Resistor Values

Operating the OPA838 in inverting mode with higher RF values increases response peaking due to the loss of phase margin effect. In the inverting case, a pair of capacitors can flatten the response at the cost of lower closed-loop bandwidth. Figure 8-4 shows an example with a 20-kΩ RF value at an inverting gain of –5 V/V (noise gain = 6 V/V) with optional capacitors (CF and CG). Figure 8-4 shows optional bias current cancellation elements on the noninverting input. The total resistance value matches the parallel combination of RG || RF, which reduces the DC output error term due to bias current to IOS × RF. The 10-nF capacitor is added across the larger part of this bias current canceling resistance to filter noise and the 20 Ω is split out to isolate the capacitor self resonance from the noninverting input. Figure 8-5 illustrates the small-signal response shape with and without these capacitors. The feedback capacitor (CF), is selected to set a desired closed-loop bandwidth with RF. CG is added to ground to shape the noise gain up over frequency to be greater than or equal to 6 V/V at higher frequencies. In this example, that higher frequency noise gain is 1 + 6 / 1.2 = 6 V/V, adding the 1-pF device common-mode capacitance to the external 5 pF. Using the capacitors to set the feedback ratio removes the pole produced in the feedback driving from purely resistive source to the inverting parasitic capacitance.

GUID-87A073BB-1989-498D-9108-75DB9E5D8CCD-low.gifFigure 8-4 G = –5 V/V With Optional Compensation
GUID-612BED55-9A90-4108-9F40-947671FB7D2D-low.gifFigure 8-5 Inverting Response With and Without Compensation