ZHCSQB5B April   2019  – February 2023 DLP480RE

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Optical Interface and System Image Quality
        1. 7.5.1.1 Numerical Aperture and Stray Light Control
        2. 7.5.1.2 Pupil Match
        3. 7.5.1.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 DMD Die Temperature Sensing
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
        1. 10.2.3.1 Voltage Signals
  11. 11Device and Documentation Support
    1. 11.1 第三方产品免责声明
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 支持资源
    6. 11.6 Trademarks
    7. 11.7 静电放电警告
    8. 11.8 术语表
      1.      Mechanical, Packaging, and Orderable Information

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9.2 DMD Power Supply Power-Down Procedure

GUID-E35514CA-A204-4623-AD88-6123934D2306-low.gif
B. To prevent excess current, the supply voltage difference |VOFFSET – VBIAS| must be less than specified limit in GUID-BE8D87C3-9261-414C-9DA7-46DF77EDAB95.html#GUID-BE8D87C3-9261-414C-9DA7-46DF77EDAB95.
C. To prevent excess current, the supply voltage difference |VBIAS – VRESET| must be less than specified limit in GUID-BE8D87C3-9261-414C-9DA7-46DF77EDAB95.html#GUID-BE8D87C3-9261-414C-9DA7-46DF77EDAB95.
D. VBIAS must power up after VOFFSET has powered up, per the Delay1 specification in Table 9-1
E. PG_OFFSET must turn off after EN_OFFSET has turned off, per the Delay2 specification in Table 9-1.
F. DLP® controller software enables the DMD power supplies to turn on after RESET_OEZ is at logic high.
G. DLP® controller software initiates the global VBIAS command.
H. After the DMD micromirror park sequence is complete, the DLP® controller software initiates a hardware power-down that activates PWRDNZ and disables VBIAS, VRESET and VOFFSET.
I. Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP® controller hardware, EN_OFFSET may turn off after PG_OFFSET has turned off. The OEZ signal goes high prior to PG_OFFSET turning off to indicate the DMD micromirror has completed the emergency park procedures.
Figure 9-1 DMD Power Supply Requirements
Table 9-1 DMD Power-Supply Requirements
PARAMETERDESCRIPTIONMINNOMMAXUNIT
Delay1Delay from VOFFSET settled at recommended operating voltage to VBIAS and VRESET power up12ms
Delay2PG_OFFSET hold time after EN_OFFSET goes low100ns