ZHCSQB5B
April 2019 – February 2023
DLP480RE
PRODUCTION DATA
1
特性
2
应用
3
说明
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
Storage Conditions
6.3
ESD Ratings
6.4
Recommended Operating Conditions
6.5
Thermal Information
6.6
Electrical Characteristics
6.7
Capacitance at Recommended Operating Conditions
6.8
Timing Requirements
6.9
System Mounting Interface Loads
6.10
Micromirror Array Physical Characteristics
6.11
Micromirror Array Optical Characteristics
6.12
Window Characteristics
6.13
Chipset Component Usage Specification
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Power Interface
7.3.2
Timing
7.4
Device Functional Modes
7.5
Optical Interface and System Image Quality Considerations
7.5.1
Optical Interface and System Image Quality
7.5.1.1
Numerical Aperture and Stray Light Control
7.5.1.2
Pupil Match
7.5.1.3
Illumination Overfill
7.6
Micromirror Array Temperature Calculation
7.7
Micromirror Landed-On/Landed-Off Duty Cycle
7.7.1
Definition of Micromirror Landed-On/Landed-Off Duty Cycle
7.7.2
Landed Duty Cycle and Useful Life of the DMD
7.7.3
Landed Duty Cycle and Operational DMD Temperature
7.7.4
Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
8.3
DMD Die Temperature Sensing
9
Power Supply Recommendations
9.1
DMD Power Supply Power-Up Procedure
9.2
DMD Power Supply Power-Down Procedure
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
10.2.1
Layers
10.2.2
Impedance Requirements
10.2.3
Trace Width, Spacing
10.2.3.1
Voltage Signals
11
Device and Documentation Support
11.1
第三方产品免责声明
11.2
Device Support
11.2.1
Device Nomenclature
11.2.2
Device Markings
11.3
Documentation Support
11.3.1
Related Documentation
11.4
Receiving Notification of Documentation Updates
11.5
支持资源
11.6
Trademarks
11.7
静电放电警告
11.8
术语表
Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
FXG|257
MCSS005A
散热焊盘机械数据 (封装 | 引脚)
订购信息
zhcsqb5b_oa
9.1
DMD Power Supply Power-Up Procedure
During power-up, VCC must always start and settle before VOFFSET plus Delay1 specified in
Table 9-1
, VBIAS, and VRESET voltages are applied to the DMD.
During power-up, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be within the specified limit shown in
GUID-BE8D87C3-9261-414C-9DA7-46DF77EDAB95.html#GUID-BE8D87C3-9261-414C-9DA7-46DF77EDAB95
.
During power-up, there is no requirement for the relative timing of VRESET with respect to VBIAS.
Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the requirements specified in
GUID-2F34D9CC-C4C8-4DC0-A0B1-5201327237C6.html#GUID-2F34D9CC-C4C8-4DC0-A0B1-5201327237C6
, in
GUID-BE8D87C3-9261-414C-9DA7-46DF77EDAB95.html#GUID-BE8D87C3-9261-414C-9DA7-46DF77EDAB95
, and in
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.
During power-up, LVCMOS input pins must not be driven high until after VCC have settled at operating voltages listed in
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.