ZHCSQB5B April 2019 – February 2023 DLP480RE
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 Storage Conditions
- 6.3 ESD Ratings
- 6.4 Recommended Operating Conditions
- 6.5 Thermal Information
- 6.6 Electrical Characteristics
- 6.7 Capacitance at Recommended Operating Conditions
- 6.8 Timing Requirements
- 6.9 System Mounting Interface Loads
- 6.10 Micromirror Array Physical Characteristics
- 6.11 Micromirror Array Optical Characteristics
- 6.12 Window Characteristics
- 6.13 Chipset Component Usage Specification
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
5 Pin Configuration and Functions
Figure 5-1 Series 410257-pin FXGBottom View|
CAUTION:
To ensure reliable, long-term operation of the .48-inch WUXGA S410 DMD, it is critical to properly manage the layout and operation of the signals identified in the table below. For specific details and guidelines, refer to the PCB Design Requirements for TI DLP Standard TRP Digital Micromirror Devices application report before designing the board. |
Table 5-1 Pin Functions
| PIN | I/O(3) | SIGNAL | DATA RATE |
INTERNAL TERMINATION |
DESCRIPTION | TRACE LENGTH (mil) |
|
|---|---|---|---|---|---|---|---|
| NAME | NO. | ||||||
| D_AN(0) | C6 | NC | LVDS | DDR | Differential | No connect | 805.0 |
| D_AN(1) | C3 | ||||||
| D_AN(2) | E1 | ||||||
| D_AN(3) | C4 | ||||||
| D_AN(4) | D1 | ||||||
| D_AN(5) | B8 | ||||||
| D_AN(6) | F4 | ||||||
| D_AN(7) | E3 | ||||||
| D_AN(8) | C11 | ||||||
| D_AN(9) | F3 | ||||||
| D_AN(10) | K4 | ||||||
| D_AN(11) | H3 | ||||||
| D_AN(12) | J3 | ||||||
| D_AN(13) | C13 | ||||||
| D_AN(14) | A5 | ||||||
| D_AN(15) | A3 | ||||||
| D_AP(0) | C7 | NC | LVDS | DDR | Differential | No connect | 805.0 |
| D_AP(1) | C2 | ||||||
| D_AP(2) | E2 | ||||||
| D_AP(3) | B4 | ||||||
| D_AP(4) | C1 | ||||||
| D_AP(5) | B7 | ||||||
| D_AP(6) | E4 | ||||||
| D_AP(7) | D3 | ||||||
| D_AP(8) | C12 | ||||||
| D_AP(9) | F2 | ||||||
| D_AP(10) | J4 | ||||||
| D_AP(11) | G3 | ||||||
| D_AP(12) | J2 | ||||||
| D_AP(13) | C14 | ||||||
| D_AP(14) | A6 | ||||||
| D_AP(15) | A4 | ||||||
| D_BN(0) | N4 | NC | LVDS | DDR | Differential | No connect | 805.0 |
| D_BN(1) | Z11 | ||||||
| D_BN(2) | W4 | ||||||
| D_BN(3) | W10 | ||||||
| D_BN(4) | L1 | ||||||
| D_BN(5) | V8 | ||||||
| D_BN(6) | W6 | ||||||
| D_BN(7) | M1 | ||||||
| D_BN(8) | R4 | ||||||
| D_BN(9) | W1 | ||||||
| D_BN(10) | U4 | ||||||
| D_BN(11) | V2 | ||||||
| D_BN(12) | Z5 | ||||||
| D_BN(13) | N3 | ||||||
| D_BN(14) | Z2 | ||||||
| D_BN(15) | L4 | ||||||
| D_BP(0) | M4 | NC | LVDS | DDR | Differential | No connect | 805.0 |
| D_BP(1) | Z12 | ||||||
| D_BP(2) | Z4 | ||||||
| D_BP(3) | Z10 | ||||||
| D_BP(4) | L2 | ||||||
| D_BP(5) | V9 | ||||||
| D_BP(6) | W7 | ||||||
| D_BP(7) | N1 | ||||||
| D_BP(8) | P4 | ||||||
| D_BP(9) | V1 | ||||||
| D_BP(10) | T4 | ||||||
| D_BP(11) | V3 | ||||||
| D_BP(12) | Z6 | ||||||
| D_BP(13) | N2 | ||||||
| D_BP(14) | Z3 | ||||||
| D_BP(15) | L3 | ||||||
| D_CN(0) | H27 | I | LVDS | DDR | Differential | Data negative | 805.0 |
| D_CN(1) | A20 | ||||||
| D_CN(2) | H28 | ||||||
| D_CN(3) | K28 | ||||||
| D_CN(4) | K30 | ||||||
| D_CN(5) | C23 | ||||||
| D_CN(6) | G27 | ||||||
| D_CN(7) | J30 | ||||||
| D_CN(8) | B24 | ||||||
| D_CN(9) | A21 | ||||||
| D_CN(10) | A27 | ||||||
| D_CN(11) | C29 | ||||||
| D_CN(12) | A26 | ||||||
| D_CN(13) | C25 | ||||||
| D_CN(14) | A29 | ||||||
| D_CN(15) | C30 | ||||||
| D_CP(0) | J27 | I | LVDS | DDR | Differential | Data positive | 805.0 |
| D_CP(1) | A19 | ||||||
| D_CP(2) | H29 | ||||||
| D_CP(3) | K27 | ||||||
| D_CP(4) | K29 | ||||||
| D_CP(5) | C22 | ||||||
| D_CP(6) | F27 | ||||||
| D_CP(7) | H30 | ||||||
| D_CP(8) | B25 | ||||||
| D_CP(9) | B21 | ||||||
| D_CP(10) | B27 | ||||||
| D_CP(11) | C28 | ||||||
| D_CP(12) | A25 | ||||||
| D_CP(13) | C24 | ||||||
| D_CP(14) | A28 | ||||||
| D_CP(15) | B30 | ||||||
| D_DN(0) | V25 | I | LVDS | DDR | Differential | Data negative | 805.0 |
| D_DN(1) | V28 | ||||||
| D_DN(2) | T30 | ||||||
| D_DN(3) | V27 | ||||||
| D_DN(4) | U30 | ||||||
| D_DN(5) | W23 | ||||||
| D_DN(6) | R27 | ||||||
| D_DN(7) | T28 | ||||||
| D_DN(8) | V20 | ||||||
| D_DN(9) | R28 | ||||||
| D_DN(10) | L27 | ||||||
| D_DN(11) | N28 | ||||||
| D_DN(12) | M28 | ||||||
| D_DN(13) | V18 | ||||||
| D_DN(14) | Z26 | ||||||
| D_DN(15) | Z28 | ||||||
| D_DP(0) | V24 | I | LVDS | DDR | Differential | Data positive | 805.0 |
| D_DP(1) | V29 | ||||||
| D_DP(2) | T29 | ||||||
| D_DP(3) | W27 | ||||||
| D_DP(4) | V30 | ||||||
| D_DP(5) | W24 | ||||||
| D_DP(6) | T27 | ||||||
| D_DP(7) | U28 | ||||||
| D_DP(8) | V19 | ||||||
| D_DP(9) | R29 | ||||||
| D_DP(10) | M27 | ||||||
| D_DP(11) | P28 | ||||||
| D_DP(12) | M29 | ||||||
| D_DP(13) | V17 | ||||||
| D_DP(14) | Z25 | ||||||
| D_DP(15) | Z27 | ||||||
| SCTRL_AN | G1 | NC | LVDS | DDR | Differential | No connect | 805.0 |
| SCTRL_AP | F1 | ||||||
| SCTRL_BN | V5 | ||||||
| SCTRL_BP | V4 | ||||||
| SCTRL_CN | C26 | I | LVDS | DDR | Differential | Serial control negative | 805.0 |
| SCTRL_CP | C27 | I | LVDS | DDR | Differential | Serial control positive | 805.0 |
| SCTRL_DN | P30 | I | LVDS | DDR | Differential | Serial control negative | 805.0 |
| SCTRL_DP | R30 | I | LVDS | DDR | Differential | Serial control positive | 805.0 |
| DCLK_AN | H2 | NC | LVDS | Differential | No connect | 805.0 | |
| DCLK_AP | H1 | ||||||
| DCLK_BN | V6 | ||||||
| DCLK_BP | V7 | ||||||
| DCLK_CN | D27 | I | LVDS | Differential | Clock negative | 805.0 | |
| DCLK_CP | E27 | I | LVDS | Differential | Clock positive | 805.0 | |
| DCLK_DN | N29 | I | LVDS | Differential | Clock negative | 805.0 | |
| DCLK_DP | N30 | I | LVDS | Differential | Clock positive | 805.0 | |
| SCPCLK | A10 | I | LVCMOS | Pulldown | Serial communications port clock. Active only when SCPENZ is logic low | ||
| SCPDI | A12 | I | LVCMOS | SDR | Pulldown | Serial communications port Data Input. Synchronous to SCPCLK rising edge | |
| SCPENZ | C10 | I | LVCMOS | Pulldown | Serial communications port enable active low | ||
| SCPDO | A11 | O | LVCMOS | SDR | Serial communications port output | ||
| RESET_ADDR(0) | Z13 | I | LVCMOS | Pulldown | Reset driver address select | ||
| RESET_ADDR(1) | W13 | ||||||
| RESET_ADDR(2) | V10 | ||||||
| RESET_ADDR(3) | W14 | ||||||
| RESET_MODE(0) | W9 | I | LVCMOS | Pulldown | Reset driver mode select | ||
| RESET_SEL(0) | V14 | Reset driver level select | |||||
| RESET_SEL(1) | Z8 | Reset driver level select | |||||
| RESET_STROBE | Z9 | I | LVCMOS | Pulldown | Rising edge latches in RESET_ADDR, RESET_MODE, and RESET_SEL | ||
| PWRDNZ | A8 | I | LVCMOS | Pulldown | Active low device reset | ||
| RESET_OEZ | W15 | I | LVCMOS | Pullup | Active low output enable for internal reset driver circuits | ||
| RESET_IRQZ | V16 | O | LVCMOS | Active low output interrupt to DLP® display controller | |||
| EN_OFFSET | C9 | O | LVCMOS | Active high enable for external VOFFSET regulator | |||
| PG_OFFSET | A9 | I | LVCMOS | Pullup | Active low fault from external VOFFSET regulator | ||
| TEMP_N | B18 | Analog | Temperature sensor diode cathode | ||||
| TEMP_P | B17 | Analog | Temperature sensor diode anode | ||||
| RESERVED | D12, D13, D14, D15, D16, D17, D18, D19, U12, U13, U14, U15 | NC | Analog | Pulldown | Do not connect on the printed circuit board (PCB). No connect. No electrical connections from CMOS bond pad to package pin | ||
| No Connect | U16, U17, U18, U19 | NC | No connect. No electrical connection from CMOS bond pad to package pin | ||||
| RESERVED_BA | W11 | O | LVCMOS | Do not connect on the printed circuit board (PCB) | |||
| RESERVED_BB | B11 | ||||||
| RESERVED_BC | Z20 | ||||||
| RESERVED_BD | C18 | ||||||
| RESERVED_PFE | A18 | I | LVCMOS | Pulldown | Connect to ground on the printed circuit board (PCB) | ||
| RESERVED_TM | C8 | ||||||
| RESERVED_TP0 | Z19 | I | Analog | Do not connect on the printed circuit board (PCB) | |||
| RESERVED_TP1 | W20 | ||||||
| RESERVED_TP2 | W19 | ||||||
| VBIAS(1) | C15, C16, V11, V12 | P | Analog | Supply voltage for positive bias level of micromirror reset signal | |||
| VRESET(1) | G4, H4, J1, K1 | P | Analog | Supply voltage for negative reset level of micromirror reset signal | |||
| VOFFSET(1) | A30, B2, M30, Z1, Z30 | P | Analog | Supply voltage for HVCMOS logic. Supply voltage for positive offset level of micromirror reset signal. Supply voltage for stepped high voltage at micromirror address electrodes | |||
| VCC(1) | A24, A7, B10, B13, B16, B19, B22, B28, B5, C17, C20, D4, J29, K2, L29, M2, N27, U27, V13, V15, V22, W17, W21, W26, W29, W3, Z18, Z23, Z29, Z7 | P | Analog | Supply voltage for LVCMOS core. Supply voltage for positive offset level of micromirror reset signal during Power down. Supply voltage for normal high level at micromirror address electrodes | |||
| VSS(2) | A13, A22, A23, B12, B14, B15, B20, B23, B26, B29, B3, B6, B9, C19, C21, C5, D2, G2, J28, K3, L28, L30, M3, P27, P29, U29, V21, V23, V26, W12, W16, W18, W2, W22, W25, W28, W30, W5, W8, Z21, Z22, Z24 | G | Device ground. Common return for all power | ||||
(1) VBIAS, VCC, VOFFSET, and
VRESET power supplies must be connected for proper DMD
operation.
(2) VSS must be connected for proper DMD operation.
(3) I = Input, O = Output, P = Power, G = Ground, NC = No
connect