AM62P-Q1
Processor Cores:
- Up to Quad 64-bit Arm
Cortex-A53 microprocessor subsystem at up to 1.4GHz
- Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
- Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
- Single-core Arm
Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
- 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
- 512KB SRAM with SECDED ECC
- Single-core Arm
Cortex-R5F at up to 800MHz, integrated to support Device Management
- 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
Multimedia:
- Display subsystem
- Triple display support over OLDI
(LVDS) (1x OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI
- OLDI-SL (Single Link): up to 1920 x 1080 at 60fps (165MHZ Pixel Clock)
- OLDI-DL (Dual Link): up to 3840 x 1080 at 60fps (150MHz Pixel Clock)
- MIPI DSI: with 4 Lane MIPI® D-PHY supports up to 3840 x 1080 at 60fps (300MHz Pixel Clock)
- DPI (24-bit RGB parallel interface): up to 1920 x 1080 at 60fps (165MHz pixel clock)
- Four display pipelines with hardware overlay support. A maximum of two display pipelines may be used per display.
- Supports safety features such as freeze frame detection and data correctness check
- Triple display support over OLDI
(LVDS) (1x OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI
- 3D Graphics Processing Unit
- IMG BXS-4-64 with 256KB cache
- Up to 50GFLOPS
- Single shader core
- OpenGL ES3.2 and Vulkan 1.2 API support
- One Camera Serial Interface (CSI-2) Receiver with 4
Lane D-PHY
- MIPI® CSI-2 v1.3 Compliant + MIPI D-PHY 1.2
- Support for 1,2,3 or 4 data lane mode up to 2.5Gbps per lane
- ECC verification/correction with CRC check + ECC on RAM
- Virtual Channel support (up to 16)
- Ability to write stream data directly to DDR via DMA
- Video Encoder/Decoder
- Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
- Support for H.264 BaseLine/Main/High Profiles at Level 5.2
- Support for up to 4K UHD resolution
(3840 × 2160)
- Up to 400MPixels/s operation, with reduced clocking options available for lower power applications with lower performance needs
Memory Subsystem:
- Up to 1.09MB of On-chip
RAM
- 64KB of On-Chip RAM (OCRAM) with SECDED ECC, can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
- 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
- 176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
- 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
- 64KB of On-chip RAM with SECDED ECC in Device Manager Subsystem
- DDR Subsystem (DDRSS)
- Supports LPDDR4 memory type
- 32-bit data bus with inline ECC
- Supports speeds up to 3733MT/s
- Max size of 8GB
Functional Safety:
-
Functional Safety-Compliant targeted [Automotive]
- Developed for functional safety applications
- Documentation will be available to aid ISO 26262 functional safety system design
- Systematic capability up to ASIL D targeted
- Hardware integrity up to ASIL B targeted
- Safety-related certification
- ISO 26262 by TÜV SÜD planned
- AEC - Q100 qualified [Automotive]
Security:
- Secure boot supported
- Hardware-enforced Root-of-Trust (RoT)
- Support to switch RoT via backup key
- Support for takeover protection, IP protection, and anti-roll back protection
- Trusted Execution Environment (TEE)
supported
- Arm TrustZone based TEE
- Extensive firewall support for isolation
- Secure watchdog/timer/IPC
- Secure storage support
- Replay Protected Memory Block (RPMB) support
- Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
- Cryptographic acceleration supported
- Session-aware cryptographic engine
with ability to auto-switch key-material based on incoming data stream
- Supports cryptographic cores
- AES – 128-/192-/256-Bit key sizes
- SHA2 – 224-/256-/384-/512-Bit key sizes
- DRBG with true random number generator
- PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
- Session-aware cryptographic engine
with ability to auto-switch key-material based on incoming data stream
- Debugging security
- Secure software controlled debug access
- Security aware debugging
High-Speed Interfaces:
- Integrated Ethernet switch supporting
(total 2 external ports)
- RMII(10/100) or RGMII (10/100/1000)
- IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
- Clause 45 MDIO PHY management
- Packet Classifier based on ALE engine with 512 classifiers
- Priority based flow control
- Time Sensitive Networking (TSN) support
- Four CPU H/W interrupt Pacing
- IP/UDP/TCP checksum offload in hardware
- Two USB2.0 Ports
- Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
- Integrated USB VBUS detection
General Connectivity:
- 9x Universal Asynchronous Receiver-Transmitters (UART)
- 5x Serial Peripheral Interface (SPI) controllers
- 6x Inter-Integrated Circuit (I2C) ports
- 3x Multichannel Audio Serial Ports
(McASP)
- Transmit and Receive Clocks up to 50MHz
- Up to 4/6/16 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
- Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
- Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
- FIFO Buffers for Transmit and Receive (256 Bytes)
- Support for audio reference output clock
- 3x enhanced PWM modules (ePWM)
- 3x enhanced Quadrature Encoder Pulse modules (eQEP)
- 3x enhanced Capture modules (eCAP)
- General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
- 4x Controller Area Network (CAN) modules
with CAN-FD support
- Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
- Full CAN-FD support (up to 64 data bytes)
- Parity/ECC check for Message RAM
- Speed up to 8Mbps
Media and Data Storage:
- 3x Multi-Media Card/Secure Digital (MMC/SD/SDIO) interfaces
- 1x 8-bit eMMC interface up to:
- HS200 for non-Q1 devices
- HS400 for Q1 devices
- 2x 4-bit SD/SDIO interfaces up to UHS-I
- Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
- 1x 8-bit eMMC interface up to:
- 1× General-Purpose Memory Controller
(GPMC) up to 133MHz
- Flexible 8- and 16-bit Asynchronous Memory Interface with up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
- Uses BCH code to support 4-, 8-, or 16-bit ECC
- Uses Hamming code to support 1-bit ECC
- Error Locator Module (ELM)
- Used with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
- Supports 4-, 8-, and 16-bit per 512-Byte block error location based on BCH algorithms
- OSPI/QSPI with DDR / SDR support
- Support for Serial NAND and Serial NOR Flash devices
- 4GBytes memory address support
- XIP mode with optional on-the-fly encryption
Power Management:
- Low-power modes supported by Device
Manager:
- Partial IO support for CAN/GPIO/UART wakeup
- I/O Only + DDR in Self Refresh for Suspend to RAM
- DeepSleep
- MCU Only
- Standby
- Dynamic frequency scaling
Optimal Power Management Solution:
- Recommended TI Power Management ICs (PMIC)
- Supports up to Automotive ASIL-B functional safety when powering the AEC – Q100 qualified AM62P-Q1 device
- Companion PMIC is specially designed to meet power supply requirements
- Flexible mapping and factory programmed configurations to support different use cases
Boot Options:
- UART
- I2C EEPROM
- OSPI/QSPI Flash
- GPMC NOR/NAND Flash
- SD Card
- eMMC
- USB (host) Mass storage
- USB (device) boot from external host (DFU mode)
- Ethernet
Technology / Package:
- 16nm FinFET technology
- 17mm x 17mm, 0.65/0.8mm pitch with VCA, 466-pin FCBGA
The AM62Px (P = Plus) is an extension of the existing Sitara™ AM62x low-cost family of application processors built for high-performance embedded 3D display applications. Scalable Arm® Cortex®-A53 performance and embedded features, such as: multi-screen high-definition display support, 3D-graphics acceleration, 4K video acceleration, and extensive peripherals make the AM62Px well-suited for a broad range of automotive and industrial applications, including automotive digital instrumentation, automotive displays, industrial HMI, and more.
Key features and benefits:
- Focus on innovation and fast development with Linux and Android™ SDKs accompanied with real-time functional safety and security SDKs.
- Address next wave of HMI designs with new generation of 3D GPU and 4K video acceleration.
- Enhance your design connectivity with an extensive set of automotive and high-speed IOs, including: 4x CAN-FD, 3-port Gigabit Ethernet switch (two external ports) with TSN support, and two USB2.0 ports.
- Supports the latest cybersecurity requirements with the built-in Hardware Security Module (HSM).
- Provides intelligent features, such as: facial recognition and touchless HMI with Arm® Cortex®-A53 CPUs and open-source AI software and tools
The AM62Px processors comply with the AEC - Q100 automotive standard. ASIL-B functional safety requirements can be addressed using an integrated Arm Cortex-R5F core and dedicated peripherals, which can all be isolated from the rest of the processor.
Products in the AM62Px processor family:
AM62P-Q1 – Automotive digital instrumentation SoC with scalable Arm Cortex-A53 performance, multi high-definition display support, 3D GPU and 4K video acceleration.
Featured design resources:
- Hardware Evaluation Module (EVM) - SK-AM62P-LP
- Software Development Kit (SDK) - PROCESSOR-SDK-AM62P
- Linux Academy
技术文档
设计与开发
电源解决方案
查找适用于 AM62P-Q1 的电源解决方案。TI 提供适用于 TI 和非 TI 片上系统 (SoC)、处理器、微控制器、传感器和现场可编程门阵列 (FPGA) 的电源解决方案。
SK-AM62P-LP — AM62P 入门套件评估模块
SK-AM62P-LP 入门套件 (SK) 评估模块 (EVM) 围绕我们的 AM62P 显示处理器而构建，该处理器包含可扩展的 Arm® Cortex®-A53 性能和嵌入式功能，如三路高清显示支持、高性能 3D-GPU、4K 视频加速和大量外设。SK-AM62P-LP 适合那些希望开发汽车和工业应用（包括汽车数字仪表、汽车显示屏、工业 HMI 等）的人员。
SK-AM62P-LP 包含可支持多达 3 个屏幕的多个显示连接器、一个移动产业处理器接口 (MIPI®) CSI-2 摄像头连接器、一个用于 WiFi 或蓝牙模块的 M.2 连接器、2 个千兆位以太网端口、用于调试输出的 UART 到 (...)
TMDSEMU110-U — XDS110 JTAG 调试探针
德州仪器 (TI) 的 XDS110 是一款适用于 TI 嵌入式处理器的新型调试探针（仿真器）。XDS110 取代了 XDS100 系列，同时在单个仓体中支持更广泛的标准（IEEE1149.1、IEEE1149.7、SWD）。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 Arm® 和 DSP 处理器，所有 XDS 调试探针均支持核心和系统跟踪。 对于引脚上的内核跟踪，则需要使用 XDS560v2 PRO TRACE。
德州仪器 (TI) 的 XDS110 通过 TI 20 引脚连接器（带有适合 TI 14 引脚、Arm 10 引脚和 Arm 20 引脚的多个适配器）连接到目标板，通过 (...)
TMDSEMU200-U — XDS200 USB 调试探针
XDS200 是用于调试 TI 嵌入式器件的调试探针（仿真器）。对于大多数器件，建议使用较新、成本较低的 XDS110 (www.ti.com/tool/TMDSEMU110-U)。XDS200 在单个仓体中支持更广泛的标准（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 Arm® 和 DSP 处理器中均支持内核和系统跟踪。
XDS200 通过 TI 20 引脚连接器（带有适用于 TI 14 引脚、Arm Cortex® 10 引脚和 Arm 20 引脚的多个适配器）连接到目标板，并通过 USB2.0 高速 (...)
TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网
XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针（仿真器）的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。
XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件，通过捕获相关器件级信息，获得准确的总线性能活动和吞吐量，并对内核和外设进行电源管理。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS (...)
LB-3P-TRACE32-ARM — 适用于基于 Arm® 的微控制器和处理器的 Lauterbach TRACE32® 调试和跟踪系统
Lauterbach TRACE32® 工具是一套先进的硬件和软件组件，开发人员可通过它分析、优化和认证各种基于 Arm® 的微控制器和处理器。这套全球知名的嵌入式系统和 SoC 调试和跟踪解决方案是所有开发阶段（从器件前开发一直到产品认证和现场故障排查）的理想解决方案。Lauterbach 工具直观的模块化设计可为工程师提供当今最高的可用性能，并提供可随需求变化而调整和扩展的系统。借助 TRACE32® 调试器，开发人员还可以通过单个调试接口同时调试和控制 SoC 中的任何 C28x/C29x C6x/C7x DSP 内核以及所有其他 Arm 内核，这是业界的一项独特功能。
TSK-3P-BLUEBOX — TASKING BlueBox hardware debugger
TASKING’s Debug, Trace, and Test tools offer comprehensive solutions for efficient debugging, tracing, and testing of TI's embedded systems. The scalable TASKING BlueBox debuggers allow users to easily flash, debug, and test across TI's portfolio. Development on TI hardware is made even easier with (...)
MCU-PLUS-SDK-AM62P — MCU+ SDK for AM62P – RTOS, No-RTOS
AM62P 处理器 Linux®、Android™ 和 TI MCU+ 软件开发套件 (SDK) 均为面向嵌入式处理器的统一软件平台，设置简单，可提供开箱即用的基准测试和演示。
这个 SDK 的所有版本在其适用的各个产品系列中都保持一致性，开发人员可以在各种产品中连续重复使用和开发软件。
PROCESSOR-SDK-ANDROID-AM62P — Processor SDK Android for AM62P
AM62P 处理器 Linux®、Android™ 和 TI MCU+ 软件开发套件 (SDK) 均为面向嵌入式处理器的统一软件平台，设置简单，可提供开箱即用的基准测试和演示。
这个 SDK 的所有版本在其适用的各个产品系列中都保持一致性，开发人员可以在各种产品中连续重复使用和开发软件。
PROCESSOR-SDK-LINUX-AM62P — Processor SDK Linux for AM62P
AM62P 处理器 Linux®、Android™ 和 TI MCU+ 软件开发套件 (SDK) 均为面向嵌入式处理器的统一软件平台，设置简单，可提供开箱即用的基准测试和演示。
这个 SDK 的所有版本在其适用的各个产品系列中都保持一致性，开发人员可以在各种产品中连续重复使用和开发软件。
PROCESSOR-SDK-LINUX-RT-AM62P — Processor SDK Linux RT for AM62P
AM62P 处理器 Linux®、Android™ 和 TI MCU+ 软件开发套件 (SDK) 均为面向嵌入式处理器的统一软件平台，设置简单，可提供开箱即用的基准测试和演示。
这个 SDK 的所有版本在其适用的各个产品系列中都保持一致性，开发人员可以在各种产品中连续重复使用和开发软件。
CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)
CCStudio™ 集成开发环境 (IDE) 是 TI 庞大的 CCStudio™ 开发生态系统的一部分，是面向 TI 微控制器、处理器、无线连接器件和雷达传感器的集成开发环境。CCStudio IDE 可作为桌面或基于云的应用提供。云版本无需下载大型软件。此外，由于该工具基于 Eclipse Theia 框架构建，因此该界面对 VS Code®用户来说非常熟悉。如果选择在本机使用 VS Code，可以从市场上获取适用于所选器件的 TI VS Code 扩展包。
AI 驱动的开发
CCStudio IDE 集成了行业标准 AI (...)
DDR-CONFIG-AM62P — DDR Configuration Tool
K3-RESOURCE-CONFIGURATION — Resource partitioning tool for multi core SOCs
PRU-CQKIT — PRU Safety Compiler Qualification Kit
为帮助客户验证 TI ARM®、C28/CLA、C29、C6000™ 或 C7000™ C/C++ 编译器的使用符合功能和安全标准，我们开发了 TI 编译器资质审核套件。
提供两种资质审核套件类型：
- 安全编译器资质审核套件 (CQKIT) 可用于根据 IEC 61508、ISO 26262 和 EN 50657 进行功能安全开发。
- 安全和安保编译器资质审核套件 (CSQKIT) 可用于功能安全开发（EN 50657 更新到 EN 50716）和网络安全开发（根据 ISO 21434 标准）。
注意：每个编译器版本都只有较旧的 CQKIT 或 CSQKIT
这两种 QKIT 类型均为 (...)
SYSCONFIG — Standalone desktop version of SysConfig
CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.
SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)
TSK-3P-VX-TOOLSET — 用于 Arm 的 TASKING VX-toolset
VX-toolset 是专为特定 Cortex-M 和 Cortex-R 核心器件设计的经认证编译器工具链，适用于安全关键型嵌入式软件开发。借助 Eclipse IDE 集成、高级多核支持和 TASKING BlueBox 调试程序兼容性，VX-toolset 简化了开发。已通过 TÜV NORD 认证，符合 ISO 26262 至 ASIL D 级以及 ISO 21434 标准。
AM62P-ACADEMY — AM62P Academy
TI-DEVELOPER-ZONE — Start embedded development on your desktop or in the cloud
GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS
GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS
The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)
WHIS-3P-SAFERTOS — WITTENSTEIN SafeRTOS 预先认证的安全 RTOS
SAFERTOS® 是专为嵌入式处理器设计的独特实时操作系统。它通过了 TÜV SÜD 的 IEC 61508 SIL3 和 ISO 26262 ASILD 标准的预先认证。SAFERTOS® 是由 WHIS 的专家团队专为安全而设计的，并在全球范围内用于安全关键型应用。WHIS 和德州仪器 (TI) 合作已有十多年。在此期间，WHIS 已将 SAFERTOS® 移植到各种 TI 处理器中，支持所有常用内核，并可按需提供其他架构。SAFERTOS® 针对您的特定处理器/编译器组合进行定制，并随附完整的源代码和设计保证包，在整个设计生命周期中提供完全透明度。许多 WHIS 客户使用 (...)
CANDERA-3P-CGI-STUDIO — 适用于 AM62x Sitara™ 处理器的 Candera CGI Studio HMI 开发软件
EB-3P-TRESOS — Elektrobit EB tresos Classic AUTOSAR 软件
凭借在基础软件领域数十年的经验，Elektrobit 的 EB tresos 产品系列和定制的 Classic AUTOSAR 解决方案可帮助满足各个汽车制造商的特定要求，为他们提供先进的软件。对于每个工程，Elektrobit 都能提供合适的解决方案来满足汽车 AUTOSAR 需求，从符合 OSEK-/VDX 标准的基础软件到基于 Classic AUTOSAR 的多核和功能安全系统，不一而足。
DDR-MARGIN-FW — Firmware and scripts to measure system DDR margin
PROCESSOR-SDK-QNX-AM62P — Processor SDK QNX for AM62P
AM62P 处理器 Linux®、Android™ 和 TI MCU+ 软件开发套件 (SDK) 均为面向嵌入式处理器的统一软件平台，设置简单，可提供开箱即用的基准测试和演示。
这个 SDK 的所有版本在其适用的各个产品系列中都保持一致性，开发人员可以在各种产品中连续重复使用和开发软件。
RIGHTWARE-3P-KANZI — Rightware Kanzi HMI development software for AM62x Sitara™ processors
Kanzi 是汽车专用 HMI 工具链，可提供高级 HMI 体验。通过将渲染流水线和资源管理有效映射到硬件的架构，它在 AM62P 系列等嵌入式硬件上实现了出色的性能/影响比。高效优化的渲染引擎意味着可在制造商全系车型仪表组显示屏上流畅运行现代化图形。整个行业的用户体验专家和创意专业人士都喜欢其令人印象深刻的设计能力。全球已有 50 多家 OEM 在生产中采用。
VCTR-3P-MICROSAR — 适用于微控制器和高性能计算机 (HPC) 的 Vector MICROSAR AUTOSAR 软件
MICROSAR 和 DaVinci 产品系列凭借适用于微控制器和 HPC 的先进嵌入式软件和强大的开发工具简化了 ECU 开发。利用先进的基础设施软件，即可为 ECU 奠定良好基础，并使用相关工具简化所有配套开发任务。MICROSAR 嵌入式软件是按照 AUTOSAR classic 和 adaptive 等相关标准开发的。根据 ISO 26262 高达 ASIL D 的安全标准，该软件还适用于安全相关应用。此外，智能网络安全功能可保护控制单元免受未经授权的访问和操纵。Vector 涵盖汽车和其他工业应用的所有用例。对于具有高性能计算机的软件定义车辆 (...)
AM62P-EMMC-BIT-PATTERN-SIM-TOOL — AM62P EVM eMMC HS400 SI 仿真位模式文本文件
AM62P-PET-CALC — AM62P Power Estimation Tool
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| FCBGA (AMH) | 466 | Ultra Librarian |
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