TDA4APE-Q1

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具有四核 Arm® Cortex®-A72、16 TOPS AI 和 C7xDSP 的 SoC，适用于视觉感知和分析

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数据表

document-pdfAcrobat TDA4VPE-Q1, TDA4APE-Q1 Jacinto™ Automotive Processors 数据表 (Rev. C) (英语) PDF | HTML

用户指南

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J784S4 J742S2 Technical Reference Manual (Rev. E) (英语)

TDA4APE-Q1

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数据表

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产品详情

CPU

4 Arm Cortex-A72

Frequency (MHz)

2000

Coprocessors

8 Arm Cortex-R5F

Graphics acceleration

1 3D

Display type

1 DSI, 2 DSI, MIPI DPI

Protocols

Ethernet

PCIe

1 PCIe Gen 3

Hardware accelerators

C7™ NPU, Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator

Features

Vision Analytics

Operating system

AutoSAR, FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity

Security

Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection

Rating

Automotive

Power supply solution

TPS6594-Q1

Operating temperature range (°C)

-40 to 125

Edge AI enabled

Edge AI Studio enabled, Yes

CPU

4 Arm Cortex-A72

Frequency (MHz)

2000

Coprocessors

8 Arm Cortex-R5F

Graphics acceleration

1 3D

Display type

1 DSI, 2 DSI, MIPI DPI

Protocols

Ethernet

PCIe

1 PCIe Gen 3

Hardware accelerators

C7™ NPU, Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator

Features

Vision Analytics

Operating system

AutoSAR, FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity

Security

Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection

Rating

Automotive

Power supply solution

TPS6594-Q1

Operating temperature range (°C)

-40 to 125

Edge AI enabled

Edge AI Studio enabled, Yes

FCBGA (AND)

1063

729 mm² (27 mm × 27 mm)

Processor cores:

Up to Three floating point, vector C7™ DSP, up to 1.0GHz, 240GFLOPS, 768GOPS
Up to Two Deep-learning matrix multiply accelerator (MMAv2), up to 16TOPS (8b) at 1.0GHz
Up to Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
Depth and Motion Processing Accelerators (DMPAC)
Four Arm Cortex-A72 microprocessor subsystem at up to 2.0GHz
- 2MB shared L2 cache per quad-core Cortex-A72 cluster
- 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
Eight Arm Cortex-R5F MCUs at up to 1.0GHz
- 32K I-Cache, 32K D-Cache, 64K L2 TCM
- Two Arm Cortex-R5F MCUs in isolated MCU subsystem
- Six Arm Cortex-R5F MCUs in general compute partition
GPU IMG BXS-4-64, 256kB Cache, up to 800MHz, 50GFLOPS, 4GTexels/s (TDA4VPE)
Custom-designed interconnect fabric supporting near max processing entitlement
Memory subsystem:
Up to 8MB of on-chip L3 RAM with ECC and coherency
- ECC error protection
- Shared coherent cache
- Supports internal DMA engine
Up to Two External Memory Interface (EMIF) modules with ECC
- Supports LPDDR4 memory types
- Supports speeds up to 4266MT/s
- Up to 2x32-b bus with inline ECC up to 34GB/s
General-Purpose Memory Controller (GPMC)
3x512KB on-chip SRAM in MAIN domain, protected by ECC
Functional Safety:
Functional Safety-Compliant targeted (on select part numbers)
- Developed for functional safety applications
- Documentation available to aid ISO 26262/IEC 61508 functional safety system design up to ASIL D/SIL 3
- Systematic capability up to ASIL-D/SIL-3
- Hardware integrity up to ASIL-D/SIL-3for MCU Domain
- Hardware integrity up to ASIL-B/SIL-2 for Main Domain
- Hardware integrity up to ASIL-D/SIL-3 for Extended MCU (EMCU) portion of the Main Domain
Safety-related certification
- ISO 26262/IEC 61508 certification up to ASIL D/SIL 3 by TÜV SÜD
AEC-Q100 qualified on part number variants ending in Q1
Device security (on select part numbers):
Secure boot with secure run-time support
Customer programmable root key, up to RSA-4K or ECC-512
Embedded hardware security module
Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES
High speed serial interfaces:
Integrated Ethernet switch supporting 4 external ports
- Two ports support 5Gb, 10Gb USXGMII/XFI
- All ports support 1Gb, 2.5Gb SGMII
- All ports can support QSGMII. A maximum of 1 QSGMII can be enabled and uses all 4 internal lanes
Up to 2x2L/1x4L PCI-Express (PCIe) Gen3 controllers
- Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
One USB 3.0 dual-role device (DRD) subsystem
- Enhanced SuperSpeed Gen1 Port
- Supports Type-C switching
- Independently configurable as USB host, USB peripheral, or USB DRD
Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
- MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
- CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
- CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane
Ethernet:
Two RGMII/RMII interfaces
Automotive interfaces:
Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support
Display subsystem:
Two DSI 4L TX (up to 2.5k)
One eDP/DP interface with Multi-Display Support (MST)
One DPI
Audio interfaces:
Five Multichannel Audio Serial Port (MCASP) modules
Video acceleration:
H.264/H.265 Encode/Decode, up to 960MP/s
Flash memory interfaces:
Embedded MultiMediaCard Interface ( eMMC™ 5.1)
One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
Universal Flash Storage (UFS 2.1) interface with two lanes
Two independent flash interfaces configured as
- One OSPI or HyperBus™ or QSPI flash interfaces, and
- One QSPI flash interface
System-on-Chip (SoC) architecture:
16-nm FinFET technology
27mm × 27mm, 0.8-mm pitch, 1063-pin FCBGA (AND), enables IPC class 3 PCB routing
TPS6594-Q1 Companion Power Management ICs (PMIC):
Functional Safety-Compliant support up to ASIL D/SIL 3
Flexible mapping to support different use cases

Processor cores:

Up to Three floating point, vector C7™ DSP, up to 1.0GHz, 240GFLOPS, 768GOPS
Up to Two Deep-learning matrix multiply accelerator (MMAv2), up to 16TOPS (8b) at 1.0GHz
Up to Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
Depth and Motion Processing Accelerators (DMPAC)
Four Arm Cortex-A72 microprocessor subsystem at up to 2.0GHz
- 2MB shared L2 cache per quad-core Cortex-A72 cluster
- 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
Eight Arm Cortex-R5F MCUs at up to 1.0GHz
- 32K I-Cache, 32K D-Cache, 64K L2 TCM
- Two Arm Cortex-R5F MCUs in isolated MCU subsystem
- Six Arm Cortex-R5F MCUs in general compute partition
GPU IMG BXS-4-64, 256kB Cache, up to 800MHz, 50GFLOPS, 4GTexels/s (TDA4VPE)
Custom-designed interconnect fabric supporting near max processing entitlement
Memory subsystem:
Up to 8MB of on-chip L3 RAM with ECC and coherency
- ECC error protection
- Shared coherent cache
- Supports internal DMA engine
Up to Two External Memory Interface (EMIF) modules with ECC
- Supports LPDDR4 memory types
- Supports speeds up to 4266MT/s
- Up to 2x32-b bus with inline ECC up to 34GB/s
General-Purpose Memory Controller (GPMC)
3x512KB on-chip SRAM in MAIN domain, protected by ECC
Functional Safety:
Functional Safety-Compliant targeted (on select part numbers)
- Developed for functional safety applications
- Documentation available to aid ISO 26262/IEC 61508 functional safety system design up to ASIL D/SIL 3
- Systematic capability up to ASIL-D/SIL-3
- Hardware integrity up to ASIL-D/SIL-3for MCU Domain
- Hardware integrity up to ASIL-B/SIL-2 for Main Domain
- Hardware integrity up to ASIL-D/SIL-3 for Extended MCU (EMCU) portion of the Main Domain
Safety-related certification
- ISO 26262/IEC 61508 certification up to ASIL D/SIL 3 by TÜV SÜD
AEC-Q100 qualified on part number variants ending in Q1
Device security (on select part numbers):
Secure boot with secure run-time support
Customer programmable root key, up to RSA-4K or ECC-512
Embedded hardware security module
Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES
High speed serial interfaces:
Integrated Ethernet switch supporting 4 external ports
- Two ports support 5Gb, 10Gb USXGMII/XFI
- All ports support 1Gb, 2.5Gb SGMII
- All ports can support QSGMII. A maximum of 1 QSGMII can be enabled and uses all 4 internal lanes
Up to 2x2L/1x4L PCI-Express (PCIe) Gen3 controllers
- Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
One USB 3.0 dual-role device (DRD) subsystem
- Enhanced SuperSpeed Gen1 Port
- Supports Type-C switching
- Independently configurable as USB host, USB peripheral, or USB DRD
Three CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHY
- MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
- CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
- CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane
Ethernet:
Two RGMII/RMII interfaces
Automotive interfaces:
Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support
Display subsystem:
Two DSI 4L TX (up to 2.5k)
One eDP/DP interface with Multi-Display Support (MST)
One DPI
Audio interfaces:
Five Multichannel Audio Serial Port (MCASP) modules
Video acceleration:
H.264/H.265 Encode/Decode, up to 960MP/s
Flash memory interfaces:
Embedded MultiMediaCard Interface ( eMMC™ 5.1)
One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
Universal Flash Storage (UFS 2.1) interface with two lanes
Two independent flash interfaces configured as
- One OSPI or HyperBus™ or QSPI flash interfaces, and
- One QSPI flash interface
System-on-Chip (SoC) architecture:
16-nm FinFET technology
27mm × 27mm, 0.8-mm pitch, 1063-pin FCBGA (AND), enables IPC class 3 PCB routing
TPS6594-Q1 Companion Power Management ICs (PMIC):
Functional Safety-Compliant support up to ASIL D/SIL 3
Flexible mapping to support different use cases

The TDA4VPE-Q1 TDA4APE-Q1 processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in an functional safety compliant targeted architecture make the TDA4VPE-Q1 TDA4APE-Q1 devices a great fit for several imaging, vision, radar, sensor fusion and AI applications such as: Robotics, Mobile machineries, Off-highway vehicle controller, Machine Vision, AI BOX, Gateways, Retail automation, Medical Imaging, and so on. The TDA4VPE-Q1 TDA4APE-Q1 provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview

The next generation C7™ DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. A single instance of the new “MMAv2” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.

General Compute Cores and Integration Overview

Separate four core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Four Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72’s unencumbered for applications. The integrated IMG BXS-4-64 GPU offers up to 50GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VPE-Q1 TDA4APE-Q1 family also includes an MCU island eliminating the need for an external system microcontroller.

Key Performance Cores Overview

General Compute Cores and Integration Overview

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顶层文档	类型	标题	格式选项	下载最新的英语版本		日期
*	数据表	TDA4VPE-Q1, TDA4APE-Q1 Jacinto™ Automotive Processors 数据表 (Rev. C)	PDF \| HTML			2026-8-17
*	用户指南	J784S4 J742S2 Technical Reference Manual (Rev. E)	PDF \| HTML			2025-9-9
*	勘误表	J784S4 AM69x TDA4VH TDA4AH TDA4VP TDA4AP J742S2 TDA4VPE TDA4APE 处理器器件版本 1.0	PDF \| HTML		PDF \| HTML	2026-6-12
	应用手册	TDA4 器件启动流程选项	PDF \| HTML		PDF \| HTML	2026-5-20
	产品概述	TIDLRunner：简化边缘 AI 加速处理器的自带模型开发流程	PDF \| HTML		PDF \| HTML	2026-5-19
	功能安全信息	Confirmation of Software Component Qualification for JACINTO IPC for J721E, J721S2, J7200, J784S4, and J742S2	PDF \| HTML			2026-3-19
	功能安全信息	J721E, J721S2, J7200, J784S4, and J742S2 TÜV SÜD Letter of Confirmation for Software Component Qualification				2025-10-1
	产品概述	Jacinto™ 7 安全产品概述	PDF \| HTML	英语版	PDF \| HTML	2025-10-1
	功能安全信息	J7200, J721E, J721S2, J722S, J742S2, and J784S4 SDL TÜV SÜD Functional Safety Certificate (Rev. A)				2025-9-25
	用户指南	使用 TPS6594133A-Q1 PMIC 和双通道 HCP 转换器为适用于隔离式电源组的 Jacinto TM J7 SoC 系列器件供电 (Rev. A)	PDF \| HTML	英语版 (Rev.A)	PDF \| HTML	2025-6-30
	功能安全信息	TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. D)				2025-6-17
	功能安全信息	J784S4: TDA4VH TDA4AH TDA4VP TDA4AP SN17 SN18, J742S2: TDA4VPE TDA4APE SN16 TÜV Functional Safety Certificate				2025-6-11
	用户指南	J784S4、TDA4VH、TDA4AH、TDA4VP、TDA4AP、AM69 功耗估算工具用户指南 (Rev. A)		英语版 (Rev.A)	PDF \| HTML	2025-1-16
	应用手册	Jacinto7 AM6x/TDA4x/DRA8x LPDDR4 设计指南 (Rev. F)	PDF \| HTML	英语版 (Rev.F)	PDF \| HTML	2024-8-15
	应用手册	调试 TDA4x 和 AM6x 器件上的 GPU 驱动程序问题	PDF \| HTML	英语版	PDF \| HTML	2024-6-21
	应用手册	Jacinto7 AM6x、TDA4x 和 DRA8x 高速接口设计指南 (Rev. A)	PDF \| HTML	英语版 (Rev.A)	PDF \| HTML	2024-6-5
	应用手册	MMC SW 调优算法 (Rev. A)	PDF \| HTML	英语版 (Rev.A)	PDF \| HTML	2024-5-20
	应用手册	Jacinto7 AM6x/TDA4x/DRA8x 原理图检查清单 (Rev. B)	PDF \| HTML	英语版 (Rev.B)	PDF \| HTML	2024-4-10
	应用手册	Jacinto7 HS 器件客户退货流程	PDF \| HTML	英语版	PDF \| HTML	2024-1-17
	应用手册	Jacinto 7 SoC 上的 UART 日志调试系统	PDF \| HTML	英语版	PDF \| HTML	2024-1-10
	技术文章	Building multicamera vision perception systems for ADAS domain controllers with integrated processors	PDF \| HTML			2024-1-5
	技术文章	How to deliver current beyond 100 A to an ADAS processor	PDF \| HTML			2024-1-4
	白皮书	使用高度集成的处理器设计高效的边缘 AI 系统 (Rev. A)	PDF \| HTML	英语版 (Rev.A)	PDF \| HTML	2023-4-19
	应用手册	双 TDA4x 系统解决方案	PDF \| HTML	英语版	PDF \| HTML	2022-6-3
	应用手册	在 Jacinto7 SoC 上启用 MAC2MAC 功能	PDF \| HTML	英语版		2022-6-3
	应用手册	TDA4 系列的 SPI 启用和验证	PDF \| HTML	英语版	PDF \| HTML	2022-6-3
	应用手册	TDA4 刷写技术	PDF \| HTML	英语版	PDF \| HTML	2022-4-29
	技术文章	How are sensors and processors creating more intelligent and autonomous robots?	PDF \| HTML			2022-3-29
	技术文章	How to simplify your embedded edge AI application development	PDF \| HTML			2022-1-28
	应用手册	OSPI 控制器 PHY 调优算法	PDF \| HTML	英语版	PDF \| HTML	2021-11-15
	功能安全信息	Leverage Jacinto 7 Processors Functional Safety Features for Automotive Designs (Rev. A)	PDF \| HTML			2021-10-13
	白皮书	Jacinto™ 7 处理器上的安全赋能器		英语版		2021-1-4
	白皮书	通过 Jacinto™ 7 处理器上的 MCU 集成实现差异化		英语版		2020-10-22

设计与开发

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评估板

J742S2XH01EVM — TDA4VPE 和 TDA4APE 评估模块

J742S2XH01EVM 评估模块 (EVM) 是一个用于评估 TDA4VPE-Q1 和 TDA4APE-Q1 处理器的平台，这些处理器用于整个汽车和工业市场中的视觉分析和网络应用，在多摄像头、传感器融合和高级驾驶辅助系统 (ADAS) 域控制应用中的性能尤为出色。J742S2XH01EVM 由 SDK 处理器提供支持，后者包括基础驱动程序、计算和视觉内核以及示例应用框架和演示，介绍了如何利用 Jacinto™ 7 处理器功能强大的异构架构。

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调试探针

LB-3P-TRACE32-ARM — 适用于基于 Arm® 的微控制器和处理器的 Lauterbach TRACE32® 调试和跟踪系统

Lauterbach TRACE32® 工具是一套先进的硬件和软件组件，开发人员可通过它分析、优化和认证各种基于 Arm® 的微控制器和处理器。这套全球知名的嵌入式系统和 SoC 调试和跟踪解决方案是所有开发阶段（从器件前开发一直到产品认证和现场故障排查）的理想解决方案。Lauterbach 工具直观的模块化设计可为工程师提供当今最高的可用性能，并提供可随需求变化而调整和扩展的系统。借助 TRACE32® 调试器，开发人员还可以通过单个调试接口同时调试和控制 SoC 中的任何 C28x/C29x C6x/C7x DSP 内核以及所有其他 Arm 内核，这是业界的一项独特功能。

来源：Lauterbach GmbH

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TSK-3P-BLUEBOX — TASKING BlueBox hardware debugger

TASKING’s Debug, Trace, and Test tools offer comprehensive solutions for efficient debugging, tracing, and testing of TI's embedded systems. The scalable TASKING BlueBox debuggers allow users to easily flash, debug, and test across TI's portfolio. Development on TI hardware is made even easier with (...)

来源：TASKING Germany GmbH

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软件开发套件 (SDK)

J742S2-PROCESSOR-LINUX-SDK — Linux® SDK for TDA4APE-Q1 and TDA4VPE-Q1

J742S2 处理器软件开发套件 (SDK) 实时操作系统 (RTOS) 可与 Processor SDK Linux® 或 Processor SDK QNX® 一起使用，组成适用于 Jacinto™ 平台内 TDA4APE-Q1 和 TDA4VPE-Q1 片上系统 (SoC) 的多处理器软件开发平台。

J742S2-PROCESSOR-SDK 提供了一整套软件工具和元件，可帮助用户在支持的 J742S2 SoC 上开发和部署其应用程序。Processor SDK RTOS 可与 Processor SDK Linux 或 Processor SDK QNX (...)

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软件开发套件 (SDK)

J742S2-PROCESSOR-QNX-SDK — QNX SDK for TDA4APE-Q1 and TDA4VPE-Q1

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软件开发套件 (SDK)

J742S2-PROCESSOR-RTOS-SDK — RTOS SDK for TDA4APE-Q1 and TDA4VPE-Q1

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IDE、配置、编译器或调试器

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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启动

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IDE、配置、编译器或调试器

TSK-3P-VX-TOOLSET — 用于 Arm 的 TASKING VX-toolset

VX-toolset 是专为特定 Cortex-M 和 Cortex-R 核心器件设计的经认证编译器工具链，适用于安全关键型嵌入式软件开发。借助 Eclipse IDE 集成、高级多核支持和 TASKING BlueBox 调试程序兼容性，VX-toolset 简化了开发。已通过 TÜV NORD 认证，符合 ISO 26262 至 ASIL D 级以及 ISO 21434 标准。

来源：TASKING Germany GmbH

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操作系统 (OS)

WHIS-3P-SAFERTOS — WITTENSTEIN SafeRTOS 预先认证的安全 RTOS

SAFERTOS® 是专为嵌入式处理器设计的独特实时操作系统。它通过了 TÜV SÜD 的 IEC 61508 SIL3 和 ISO 26262 ASILD 标准的预先认证。SAFERTOS® 是由 WHIS 的专家团队专为安全而设计的，并在全球范围内用于安全关键型应用。WHIS 和德州仪器 (TI) 合作已有十多年。在此期间，WHIS 已将 SAFERTOS® 移植到各种 TI 处理器中，支持所有常用内核，并可按需提供其他架构。SAFERTOS® 针对您的特定处理器/编译器组合进行定制，并随附完整的源代码和设计保证包，在整个设计生命周期中提供完全透明度。许多 WHIS 客户使用 (...)

来源：WITTENSTEIN High Integrity Systems

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应用软件和框架

J742S2-SW — J742S2 software

Software packages for Processor SDK release

支持的产品和硬件

发送申请

固件

USIT-3P-SECIC-HSM — Uni-Sentry SecIC-HSM 固件

SecIC-HSM 旨在满足 MCU/SoC 芯片所需的网络安全要求。HSM 固件可应用于汽车、新能源、光伏、机器人、医疗保健和航空等领域。提供的网络安全功能包括安全启动、安全通信 (SecOC)、安全诊断、安全存储、安全更新、安全调试和密钥管理。SecIC-HSM 的优点：一站式网络安全解决方案，兼容多个芯片系列，具备行业领先的性能，已在近 30 家 OEM 的量产车型中成功部署，累计部署量超过 300 万台。

来源：Shanghai Uni-Sentry Intelligent Technology Co., LTD

支持的产品和硬件

了解详情

固件