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参数

Topology Boost, Flyback, Forward, Full-Bridge, Half-Bridge, Push-Pull Control method Voltage VCC (Min) (V) 8 VCC (Max) (V) 40 Duty cycle (Max) (%) 90 UVLO thresholds on/off (V) Frequency (Max) (kHz) 350 Operating temperature range (C) 0 to 125 Gate drive (Typ) (A) 0.2 Features Adjustable Switching Frequency, Error Amplifier, Multi-topology, Synchronization Pin Rating Catalog open-in-new 查找其它 PWM控制器和谐振控制器

封装|引脚|尺寸

PDIP (NFG) 16 52 mm² 6.35 x 8.26 SOIC (D) 16 59 mm² 9.9 x 6 open-in-new 查找其它 PWM控制器和谐振控制器

特性

  • Fully Interchangeable With Standard LM3524 Family
  • ±1% Precision 5V Reference With Thermal Shut-Down
  • Output Current to 200 mA DC
  • 60V Output Capability
  • Wide Common Mode Input Range for Error-Amp
  • One Pulse per Period (Noise Suppression)
  • Improved Max. Duty Cycle at High Frequencies
  • Double Pulse Suppression
  • Synchronize Through Pin 3

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open-in-new 查找其它 PWM控制器和谐振控制器

描述

The LM3524D family is an improved version of the industry standard LM3524. It has improved specifications and additional features yet is pin for pin compatible with existing 3524 families. New features reduce the need for additional external circuitry often required in the original version.

The LM3524D has a ±1% precision 5V reference. The current carrying capability of the output drive transistors has been raised to 200 mA while reducing VCEsat and increasing VCE breakdown to 60V. The common mode voltage range of the error-amp has been raised to 5.5V to eliminate the need for a resistive divider from the 5V reference.

In the LM3524D the circuit bias line has been isolated from the shut-down pin. This prevents the oscillator pulse amplitude and frequency from being disturbed by shut-down. Also at high frequencies (≃300 kHz) the max. duty cycle per output has been improved to 44% compared to 35% max. duty cycle in other 3524s.

In addition, the LM3524D can now be synchronized externally, through pin 3. Also a latch has been added to insure one pulse per period even in noisy environments. The LM3524D includes double pulse suppression logic that insures when a shut-down condition is removed the state of the T-flip-flop will change only after the first clock pulse has arrived. This feature prevents the same output from being pulsed twice in a row, thus reducing the possibility of core saturation in push-pull designs.

open-in-new 查找其它 PWM控制器和谐振控制器
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技术文档

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类型 标题 下载最新的英文版本 日期
* 数据表 LM2524D/LM3524D Regulating Pulse Width Modulator 数据表 (Rev. E) 2013年 5月 2日
应用手册 AN-288 System-Oriented DC-DC Conversion Techniques (Rev. B) 2013年 5月 6日
应用手册 AN-715 LM385 Feedback Provides Regulator Isolation (Rev. A) 2013年 5月 6日
应用手册 AN-694 A DMOS 3A, 55V, H-Bridge: The LMD18200 (Rev. C) 2013年 4月 26日
应用手册 AN-272 Op Amp Booster Designs (Rev. B) 2013年 4月 23日
应用手册 Applications of the LM3524 Pulse Width Modulator (Rev. B) 2013年 4月 23日
更多文献资料 Die D/S LM3524D MDC Regulating Pulse Width Modulator 2012年 9月 25日

设计与开发

有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。

设计工具和仿真

计算工具 下载
Fly-Buck 和反激式拓扑选择器
FLYBUCK-FLYBACK-DESIGN-CALC 该工具可帮助电源工程师基于规格选择正确的隔离式直流-直流拓扑。根据所选择的拓扑,计算器还会针对设计建议正确的 IC。
特性
  • 采用隔离式拓扑,如 Fly-Buck™、Fly-Buck-Boost、DCM 和 CCM 反激式
  • 能够设计多达 6 路隔离式输出
  • 针对所需的应用设计建议 IC
  • 在设计中包含回路补偿
  • 比较每个拓扑的效率、外部组件数和变压器电流

CAD/CAE 符号

封装 引脚 下载
PDIP (NFG) 16 了解详情
SOIC (D) 16 了解详情

订购与质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/FIT 估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

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