SDAA172
March 2026
AM13E23019
1
Abstract
Trademarks
1
Introduction
2
Schematic Design
2.1
Package and Device Selection
2.2
Digital Peripherals
2.2.1
GPIO
2.2.2
XBARs
2.2.3
EPI
2.2.4
MCAN
2.2.5
UNICOMM
2.2.5.1
UART
2.2.5.2
I2C
2.2.5.3
SPI
2.3
Control Peripherals
2.3.1
eQEP and eCAP
2.3.2
Timers
2.4
Analog Peripherals
2.4.1
Choosing Analog Pins
2.4.2
Analog Voltage Reference
2.4.3
ADC Inputs
2.5
Multiplexed Peripherals
2.6
Power
2.6.1
Discrete Power Solution
2.6.2
Power Decoupling and Filtering
2.6.3
Analog Voltage Reference
2.6.4
VSS/VSSA
2.6.5
Power Consumption
2.7
Reset
2.7.1
nRST Pin
2.7.2
BSL Invoke Pin
2.7.3
WAKE from LPM Pins
2.7.4
WAKE From STOP/STANDBY Modes
2.7.5
WAKE from SHUTDOWN Mode
2.7.6
AM13E230x Hardware Platform Examples
2.8
Clocking
2.8.1
Internal Oscillators
2.8.2
External Crystal Oscillator (XTAL)
2.8.3
Digital Clock Input
2.8.4
Output Clock Generation
2.9
Debugging and Emulation
2.9.1
Debug Interfaces
2.9.1.1
JTAG and SW-DP
2.9.1.2
Trace
2.9.2
Debug Probes
2.10
Boot Interfaces
2.10.1
UART Bootloader
2.10.2
I2C Bootloader
2.10.3
MCAN Bootloader
2.11
Unused Pins
3
PCB Layout Design
3.1
Layout Design Overview
3.1.1
Recommended Layout Practices
3.1.2
Board Dimensions
3.1.3
Layer Stackup
3.1.3.1
4-Layer Stackup
3.1.3.2
6-Layer Stackup
3.2
Vias
3.3
Recommended Board Layout
3.4
Placing Components
3.5
Ground Planes
3.6
Signal Routing Traces
3.7
Thermal Considerations
4
EOS, EMI/EMC, ESD Considerations
4.1
Electrical Overstress
4.2
EMI and EMC
4.3
Electrostatic Discharge
5
Summary and Checklist
6
References
7
Revision History
Application Note
AM13E230x Hardware Design Guidelines