SDAA172 March   2026 AM13E23019

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Schematic Design
    1. 2.1  Package and Device Selection
    2. 2.2  Digital Peripherals
      1. 2.2.1 GPIO
      2. 2.2.2 XBARs
      3. 2.2.3 EPI
      4. 2.2.4 MCAN
      5. 2.2.5 UNICOMM
        1. 2.2.5.1 UART
        2. 2.2.5.2 I2C
        3. 2.2.5.3 SPI
    3. 2.3  Control Peripherals
      1. 2.3.1 eQEP and eCAP
      2. 2.3.2 Timers
    4. 2.4  Analog Peripherals
      1. 2.4.1 Choosing Analog Pins
      2. 2.4.2 Analog Voltage Reference
      3. 2.4.3 ADC Inputs
    5. 2.5  Multiplexed Peripherals
    6. 2.6  Power
      1. 2.6.1 Discrete Power Solution
      2. 2.6.2 Power Decoupling and Filtering
      3. 2.6.3 Analog Voltage Reference
      4. 2.6.4 VSS/VSSA
      5. 2.6.5 Power Consumption
    7. 2.7  Reset
      1. 2.7.1 nRST Pin
      2. 2.7.2 BSL Invoke Pin
      3. 2.7.3 WAKE from LPM Pins
      4. 2.7.4 WAKE From STOP/STANDBY Modes
      5. 2.7.5 WAKE from SHUTDOWN Mode
      6. 2.7.6 AM13E230x Hardware Platform Examples
    8. 2.8  Clocking
      1. 2.8.1 Internal Oscillators
      2. 2.8.2 External Crystal Oscillator (XTAL)
      3. 2.8.3 Digital Clock Input
      4. 2.8.4 Output Clock Generation
    9. 2.9  Debugging and Emulation
      1. 2.9.1 Debug Interfaces
        1. 2.9.1.1 JTAG and SW-DP
        2. 2.9.1.2 Trace
      2. 2.9.2 Debug Probes
    10. 2.10 Boot Interfaces
      1. 2.10.1 UART Bootloader
      2. 2.10.2 I2C Bootloader
      3. 2.10.3 MCAN Bootloader
    11. 2.11 Unused Pins
  6. 3PCB Layout Design
    1. 3.1 Layout Design Overview
      1. 3.1.1 Recommended Layout Practices
      2. 3.1.2 Board Dimensions
      3. 3.1.3 Layer Stackup
        1. 3.1.3.1 4-Layer Stackup
        2. 3.1.3.2 6-Layer Stackup
    2. 3.2 Vias
    3. 3.3 Recommended Board Layout
    4. 3.4 Placing Components
    5. 3.5 Ground Planes
    6. 3.6 Signal Routing Traces
    7. 3.7 Thermal Considerations
  7. 4EOS, EMI/EMC, ESD Considerations
    1. 4.1 Electrical Overstress
    2. 4.2 EMI and EMC
    3. 4.3 Electrostatic Discharge
  8. 5Summary and Checklist
  9. 6References
  10. 7Revision History

2.10.2 I2C Bootloader

The following I2C pins are configured by the device ROM code for programming the bootloader:

Table 2-18 I2C Pins
I2C Signal Device Signal Name Pin Name GPIO # Mux Mode
I2C SCL UC2_RX_SCL PA23 GPIO23 4
I2C SDA UC2_TX_SDA PA22 GPIO22 4

Due to the open-drain nature of I2C, the SCL and SDA pins must be pulled up to VDD using a 4.7kΩ resistor.