ZHCSJM7 April 2019 BQ79606A-Q1
PRODUCTION DATA.
COMM_UART_RC_STAT1 Register Address: 0x26B | |||||||
B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
VALIDH[7] | VALIDH[6] | VALIDH[5] | VALIDH[4] | VALIDH[3] | VALIDH[2] | VALIDH[1] | VALIDH[0] |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R | R | R | R | R | R | R | R |
VALIDH[7:0] | High byte of the valid command counter for received command frames from the UART interface. Counter saturates when COMM_UART_RC_STAT1[VALIDH] and COMM_UART_RC_STAT2[VALIDL] reach 0xFFFF. The COMM_UART_*_STAT* registers are updated and the counters are reset when the COMM_UART_RC_STAT3 register is read to ensure all counter data refers to the same period of time. |