ZHCSJM7 April 2019 BQ79606A-Q1
PRODUCTION DATA.
CONTROL2 Register Address: 0x106 | |||||||
B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
VPTAT_EN | DAISY_CHAIN_CTRL_EN | BAL_GO | TSREF_EN | OTUT_EN | OVUV_EN | AUX_ADC_GO | CELL_ADC_GO |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
RW | RW | RW | RW | RW | RW | RW | RW |
VPTAT_EN | Enables the VPTAT output to be available for ADC read. VPTAT_EN must be set to 1 before the ADC read is done to ensure the correct result. When not in use, it is recommended that VPTAT_EN is '0' to avoid any noise coupling on to internal nodes.
0: VPTAT output to ADC MUX disabled 1: VPTAT output to ADC MUX enabled |
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DAISY_CHAIN_CTRL_EN | Selects the control for the daisy chain TX and RX functions. See the "Daisy Chain Transmitter and Reciever Functionality" section for more details. Note that after enabling COMM Rx, wait for at least 100usec before start communication.
0: COMH/COML TX/RX function is controlled by hardware if DAISY_CHAIN_STAT[HW_DRV]=1 and if DAISY_CHAIN_STAT[HW_DRV]=0 then is controlled by DAISY_CHAIN_CTRL register. 1: COMH/COML TX/RX function controlled by DAISY_CHAIN_CTRL register. |
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BAL_GO | Start Cell Balancing. When written, all cell balancing configuration registers are sampled. Any changes to the configuration registers have no effect until BAL_GO bit is written.
0: Ready 1: Start cell balancing Always reads '0' |
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TSREF_EN | Enables the TSREF LDO output
0: Disables 1: Enabled |
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OTUT_EN | Enables the OT/UT comparators selected in the OTUT_CTRL register. Once enabled, any changes to the configuration registers have no effect until OTUT_EN bit is cleared and then set.
0: Ready 1: Enabled |
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OVUV_EN | Enables the OV/UV comparators selected in the OVUV_CTRL register. Once enabled, any changes to the configuration registers have no effect until OVUV_EN bit is cleared and then set.
0: Ready 1: Enabled |
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AUX_ADC_GO | Start AUX ADC conversion(s). When written, all ADC configuration registers are sampled. Any changes to the configuration registers have no effect until AUX_ADC_GO bit is written.
0: Ready 1: Start AUX ADC conversion(s) Always reads '0' |
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CELL_ADC_GO | Start CELL ADC conversion(s). When written, all ADC configuration registers are sampled. Any changes to the configuration registers have no effect until CELL_ADC_GO bit is written.
0: Ready 1: Start CELL ADC conversion(s) Always reads '0' |