In actual applications, there are some non-serious events that require only the outer switches to turn off and keep the normal operation for inner switches. Thus, the two level protection scheme is needed:

• 1st level protection: only require the outer switch (S1/S4) to shut down, S2/S3 keep normal operation
• 2nd level protection: outer switch (S1/S4) to be switched off immediately, inner switch (S2/S3) should be turned off after a defined delay

From the above point of view, 1st level protection will normally occurs before 2nd level one, with the trip trigger level lower for 1st level protection, but during the sudden over current or short circuit conditions, these two protection events might occur almost at the same time. Therefore, in either protection trigger event, the EPWM for the outer switch is required to achieve CBC protection. To simply the configuration, the two trip events can be logically OR to serve as the same source for the CBC protection. According to the ePWM X-BAR architecture, the muxes that are enabled will be intrinsically OR’d before being passed on to the respective TRIPx signal on the EPWM. If using two GPIO pins for the external protection signals, two Input X-BAR INPUTs are selected for the same TRIP source.

    // Configure INPUT X-BAR 1 as EPWM X-BAR TRIP 4 source
    XBAR_setEPWMMuxConfig(XBAR_TRIP4,XBAR_EPWM_MUX01_INPUTXBAR1);
    XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX01);
    // Configure INPUT X-BAR 2 as EPWM X-BAR TRIP 4 source
    XBAR_setEPWMMuxConfig(XBAR_TRIP4,XBAR_EPWM_MUX03_INPUTXBAR2);
    XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX03);

Note that the trip signals should change to active high with the OR logic implemented. Actually, there can be no change for the external protection circuits if designed with active low initially. Using GPxINV in GPIO register configurations can inverse the IO pin logic.

Besides, the method discussed in Section 3 is still applied for 2nd level protection, where the 2nd level trip event is selected as the CLB input for the delayed protection. However, different from Section 3.1, it is the falling edge of the trip signal that used to determine the rising moment of the expected CLB signal. Thus the completed design block diagrams should be modified as Figure 5-2.

Therefore, the expected EPWM protection logic with CLB in Figure 5-2 should be updated as shown in Figure 5-3.

As mentioned in Section 5.1, it is also possible to use internal CMPSS for the two level protection scheme, with the same sensing signal. Since there are two comparators with one CMPSS, including CMPH and CMPL, which can provide trigger signals for the two trip events, with two different references.

   CMPSS_setDACValueHigh(CMPSS1_BASE, trip_point_2);
     CMPSS_setDACValueLow(CMPSS1_BASE, trip_point_1);

    // Configure CMPSS1_CTRIPH as EPWM X-BAR TRIP 4 source
    XBAR_setEPWMMuxConfig(XBAR_TRIP4,XBAR_EPWM_MUX00_CMPSS1_CTRIPH);
    XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX00);
    // Configure CMPSS1_CTRIPL as EPWM X-BAR TRIP 4 source
    XBAR_setEPWMMuxConfig(XBAR_TRIP4,XBAR_EPWM_MUX01_CMPSS1_CTRIPL);
    XBAR_enableEPWMMux(XBAR_TRIP4, XBAR_MUX01);