SPRACR2 March   2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

 

  1.   Enabling Peripheral Expansion Applications Using the HIC
    1.     Trademarks
    2. 1 Introduction
    3. 2 HIC Configurations Overview
      1. 2.1 Access Modes
      2. 2.2 Data Width Selection
      3. 2.3 Base Address Selection
      4. 2.4 Read/write I/O Configuration
      5. 2.5 Device to Host Interrupts
        1. 2.5.1 Device Internal Events
        2. 2.5.2 Software Interrupts
    4. 3 Hardware Considerations
      1. 3.1 Common Signal Names
      2. 3.2 Address Pin Mapping
      3. 3.3 BASESEL Pin Mapping
    5. 4 Example Configuration for Pin Constrained Applications
      1. 4.1 Test Setup
      2. 4.2 Test Description
    6. 5 Example Configuration for Performance-Critical Applications
      1. 5.1 Test Setup
      2. 5.2 Test Description
    7. 6 Handling Device Reset and Low-Power Conditions
    8. 7 References
  2.   A Address Translation for Different Data Width Modes
    1.     A.1 Base Address and Offset Address Configuration

6 Handling Device Reset and Low-Power Conditions

While the Device is undergoing a reset or if the Device is under the low power mode, the Host accesses could fail without any specific signature (writes might be ignored and reads might return undefined values). If such conditions are anticipated during the application run, the application layer must implement additional data integrity checks along with the normal accesses to ensure the Device is ready for accesses.

The data integrity checks could be implemented in the following ways:

  • A simple “Interface-Active” status check, where the Host would initiate a dummy write to a H2DBUF register and read-back for correctness. If the data that is read back is the same as the written data, the Device side of the interface is active and data exchanges can be performed.
  • The data payload that is being exchanged through the mailbox registers can be padded with checksum bytes and checksum verification can be performed by the receiving node.