SPRACR2 March   2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

 

  1.   Enabling Peripheral Expansion Applications Using the HIC
    1.     Trademarks
    2. 1 Introduction
    3. 2 HIC Configurations Overview
      1. 2.1 Access Modes
      2. 2.2 Data Width Selection
      3. 2.3 Base Address Selection
      4. 2.4 Read/write I/O Configuration
      5. 2.5 Device to Host Interrupts
        1. 2.5.1 Device Internal Events
        2. 2.5.2 Software Interrupts
    4. 3 Hardware Considerations
      1. 3.1 Common Signal Names
      2. 3.2 Address Pin Mapping
      3. 3.3 BASESEL Pin Mapping
    5. 4 Example Configuration for Pin Constrained Applications
      1. 4.1 Test Setup
      2. 4.2 Test Description
    6. 5 Example Configuration for Performance-Critical Applications
      1. 5.1 Test Setup
      2. 5.2 Test Description
    7. 6 Handling Device Reset and Low-Power Conditions
    8. 7 References
  2.   A Address Translation for Different Data Width Modes
    1.     A.1 Base Address and Offset Address Configuration

2.5.1 Device Internal Events

The HIC_INT port can be directly triggered through the EVENTRIG bus by supported peripherals as listed in the Event Trigger Sources table under the HIC chapter in the device-specific technical reference manual. For example, the FSI receiver can be configured to trigger an interrupt event (FSIRX_INT1) on a data tag match and this event can be enabled to generate a HIC_INT to the Host by enabling the corresponding HICD2HINTEN.EVTRIG bit. If the HIC_INT line is connected to an interrupt capable input pin of the Host, the FSI receiver can generate a direct interrupt to the Host CPU whenever there is a data tag match on the received data, thereby eliminating any intervention from the Device CPU.

Using the Device internal interrupt mapping capability and the direct Device access mode, the Host can access the peripheral of interest (that are accessible through the HIC) as if it is available on its own memory map with interrupts mapped directly to its CPU. This is depicted in Figure 8.

spracr2-device-internal-event-usage-model-using-fsi.gifFigure 8. Device Internal Event Usage Model Using FSI