SPRACR2 March   2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

 

  1.   Enabling Peripheral Expansion Applications Using the HIC
    1.     Trademarks
    2. 1 Introduction
    3. 2 HIC Configurations Overview
      1. 2.1 Access Modes
      2. 2.2 Data Width Selection
      3. 2.3 Base Address Selection
      4. 2.4 Read/write I/O Configuration
      5. 2.5 Device to Host Interrupts
        1. 2.5.1 Device Internal Events
        2. 2.5.2 Software Interrupts
    4. 3 Hardware Considerations
      1. 3.1 Common Signal Names
      2. 3.2 Address Pin Mapping
      3. 3.3 BASESEL Pin Mapping
    5. 4 Example Configuration for Pin Constrained Applications
      1. 4.1 Test Setup
      2. 4.2 Test Description
    6. 5 Example Configuration for Performance-Critical Applications
      1. 5.1 Test Setup
      2. 5.2 Test Description
    7. 6 Handling Device Reset and Low-Power Conditions
    8. 7 References
  2.   A Address Translation for Different Data Width Modes
    1.     A.1 Base Address and Offset Address Configuration

3.1 Common Signal Names

The HIC pins are designed to be connected directly to any Host controller which supports asynchronous memory. For the Host to Device pin mapping, see the Connections section under the HIC chapter in the device-specific technical reference manual. The signal naming convention could vary between different Host controllers. Some common Host signal name variants are covered in Table 2.

Table 2. HIC Pins and Their Common Name Variants

HIC Pin Common Signal Name Variant
nCS CE
Dx DQx, IOx
nBEx DQMx, BHE/BLE, be0/1n
nOE OE , OEN, ren
nWE WE, WEN
nRDY xWAIT

The polarity of each control pin can be configured based on the Host controller’s pinout using the HICPINPOLCR register.