SPRACR2 March   2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

 

  1.   Enabling Peripheral Expansion Applications Using the HIC
    1.     Trademarks
    2. 1 Introduction
    3. 2 HIC Configurations Overview
      1. 2.1 Access Modes
      2. 2.2 Data Width Selection
      3. 2.3 Base Address Selection
      4. 2.4 Read/write I/O Configuration
      5. 2.5 Device to Host Interrupts
        1. 2.5.1 Device Internal Events
        2. 2.5.2 Software Interrupts
    4. 3 Hardware Considerations
      1. 3.1 Common Signal Names
      2. 3.2 Address Pin Mapping
      3. 3.3 BASESEL Pin Mapping
    5. 4 Example Configuration for Pin Constrained Applications
      1. 4.1 Test Setup
      2. 4.2 Test Description
    6. 5 Example Configuration for Performance-Critical Applications
      1. 5.1 Test Setup
      2. 5.2 Test Description
    7. 6 Handling Device Reset and Low-Power Conditions
    8. 7 References
  2.   A Address Translation for Different Data Width Modes
    1.     A.1 Base Address and Offset Address Configuration

2.1 Access Modes

The HIC supports two access modes through which the Host can access the Device peripherals:

  • Mailbox access mode
  • Direct access mode

For the configuration details and the programming sequences for each of these usage models, see the HIC chapter of the device-specific Technical Reference Manual.

In the direct access mode, the Host CPU can directly access the memory map of the accessible peripheral in the Device; the Host access to the peripheral does not need Device CPU intervention once configured.

In Mailbox access type, the Host access is limited to the HIC’s registers and any access to the peripheral should be facilitated via the Device’s CPU or DMA to transfer data between the peripheral registers and HIC mailboxes.

Mailbox accesses have the advantage of fixed and lower latency when compared to the direct accesses to the peripherals. This is due to the fact that Host accesses in direct access mode are routed through the Device Bus-Interconnects which may arbitrate with CPU and DMA within the device.