SPRACR2 March   2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

 

  1.   Enabling Peripheral Expansion Applications Using the HIC
    1.     Trademarks
    2. 1 Introduction
    3. 2 HIC Configurations Overview
      1. 2.1 Access Modes
      2. 2.2 Data Width Selection
      3. 2.3 Base Address Selection
      4. 2.4 Read/write I/O Configuration
      5. 2.5 Device to Host Interrupts
        1. 2.5.1 Device Internal Events
        2. 2.5.2 Software Interrupts
    4. 3 Hardware Considerations
      1. 3.1 Common Signal Names
      2. 3.2 Address Pin Mapping
      3. 3.3 BASESEL Pin Mapping
    5. 4 Example Configuration for Pin Constrained Applications
      1. 4.1 Test Setup
      2. 4.2 Test Description
    6. 5 Example Configuration for Performance-Critical Applications
      1. 5.1 Test Setup
      2. 5.2 Test Description
    7. 6 Handling Device Reset and Low-Power Conditions
    8. 7 References
  2.   A Address Translation for Different Data Width Modes
    1.     A.1 Base Address and Offset Address Configuration

3.2 Address Pin Mapping

The address pin mapping between the Host and Device could vary based on the data width modes and the addressing scheme of the Host memory controllers.

A Host controller that uses the address bit 0 to represent the least significant bit of the 8-bit word address can be directly connected to the HIC address bus for 8-bit data width mode. While in case of the 16-bit data width mode, HIC_A0 has to be connected to the address bit 1 of the Host controller, since the Host address bit 1 represents a unique 16-bit word.

An example of this type of controller would be the General Purpose Memory Controller (GPMC) of the Sitara™ AM57x processor family. Table 3 shows the address translation between the GPMC and HIC for different data width modes

Table 3. Address Pin Mapping for the Sitara GPMC Controller With HIC

Device Signal Host Signal
Data Width = 16 Data Width = 8
HIC_A0 GPMC_A1 GPMC_A0
HIC_A1 GPMC_A2 GPMC_A1
HIC_A2 GPMC_A3 GPMC_A2
HIC_A3 GPMC_A4 GPMC_A3
HIC_A4 GPMC_A5 GPMC_A4
HIC_A5 GPMC_A6 GPMC_A5
HIC_A6 GPMC_A7 GPMC_A6
HIC_A7 GPMC_A8 GPMC_A7

Some of the Host memory controllers (for example, the EMIF controller of the C2000 Device family) uses an address shifting scheme to maintain uniform memory capacity for all word sizes by supplementing the address pins with additional pins like EMxBAy. For these controllers, the Host address bit 0 represents a unique 32-bit word and, hence, the address pins of such controllers have to be connected as described in Table 4.

Table 4. Address Pin Mapping for the C2000 EMIF Controller With HIC

Device Signal Host Signal
Data Width = 16 Data Width = 8
HIC_A0 EMxBA1 EMxBA0
HIC_A1 EMxA0 EMxBA1
HIC_A2 EMxA1 EMxA0
HIC_A3 EMxA2 EMxA1
HIC_A4 EMxA3 EMxA2
HIC_A5 EMxA4 EMxA3
HIC_A6 EMxA5 EMxA4
HIC_A7 EMxA6 EMxA5