SPRACR2 March   2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

 

  1.   Enabling Peripheral Expansion Applications Using the HIC
    1.     Trademarks
    2. 1 Introduction
    3. 2 HIC Configurations Overview
      1. 2.1 Access Modes
      2. 2.2 Data Width Selection
      3. 2.3 Base Address Selection
      4. 2.4 Read/write I/O Configuration
      5. 2.5 Device to Host Interrupts
        1. 2.5.1 Device Internal Events
        2. 2.5.2 Software Interrupts
    4. 3 Hardware Considerations
      1. 3.1 Common Signal Names
      2. 3.2 Address Pin Mapping
      3. 3.3 BASESEL Pin Mapping
    5. 4 Example Configuration for Pin Constrained Applications
      1. 4.1 Test Setup
      2. 4.2 Test Description
    6. 5 Example Configuration for Performance-Critical Applications
      1. 5.1 Test Setup
      2. 5.2 Test Description
    7. 6 Handling Device Reset and Low-Power Conditions
    8. 7 References
  2.   A Address Translation for Different Data Width Modes
    1.     A.1 Base Address and Offset Address Configuration

2.3 Base Address Selection

In the direct access mode, the addressable space inside the Device is much larger while the HIC interface has a limited number of address lines. In order to efficiently address a larger space, the HIC interface breaks down the addressable space into regions.

For example, to access an address 0x8000_8040 of the Device, the region base address of 0x8000_80 is programmed in the HICBASEADDRx register and the offset value of 0x40 is extracted from the incoming 8-bit address lines.

The HIC interface provides 8 base address registers(HICDBADDRx) to configure the desired region base addresses. The HIC can quickly access different peripheral regions efficiently by selecting the corresponding HICDBADDRx. This region selection can be done in either of two ways:

  • BASE_SELECT field in the HICBASESEL register
  • HIC_BASESEL[2:0] I/O pins from the Host

This selection is controlled by the HICHOSTCR.PAGESEL register field.

The I/O based region selection (done via HIC_BASESEL[2:0] pins) enables the Host to access locations from different regions without the additional latency of configuring the HICBASESEL register between accesses. However, if the application is pin constrained, the register selection method can be used. This method requires an additional Host-Register write cycle (accesses shown in violet in Figure 4) in between for cross-region accesses.

Figure 4 and Figure 5 show the dynamic region crossing across SRAM, CAN, EPWM1 peripherals for both modes. These diagrams assume that HICDBADDR1, HICDBADDR3 and HICDBADDR6 are programmed to SRAM, CAN, EPWM1 base addresses.

spracr2-cross-region-access-with-register-basesel-select.gifFigure 4. Cross-Region Access With Register BASESEL Select
spracr2-cross-region-access-io-basesel-select.gifFigure 5. Cross-Region Access With I/O BASESEL Select

Note that the HIC_BASESEL[2:0] pins should be driven with a value of 2 to select HICDBADDR1 in the I/O pin selection mode.