SPRACR2 March   2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

 

  1.   Enabling Peripheral Expansion Applications Using the HIC
    1.     Trademarks
    2. 1 Introduction
    3. 2 HIC Configurations Overview
      1. 2.1 Access Modes
      2. 2.2 Data Width Selection
      3. 2.3 Base Address Selection
      4. 2.4 Read/write I/O Configuration
      5. 2.5 Device to Host Interrupts
        1. 2.5.1 Device Internal Events
        2. 2.5.2 Software Interrupts
    4. 3 Hardware Considerations
      1. 3.1 Common Signal Names
      2. 3.2 Address Pin Mapping
      3. 3.3 BASESEL Pin Mapping
    5. 4 Example Configuration for Pin Constrained Applications
      1. 4.1 Test Setup
      2. 4.2 Test Description
    6. 5 Example Configuration for Performance-Critical Applications
      1. 5.1 Test Setup
      2. 5.2 Test Description
    7. 6 Handling Device Reset and Low-Power Conditions
    8. 7 References
  2.   A Address Translation for Different Data Width Modes
    1.     A.1 Base Address and Offset Address Configuration

2.2 Data Width Selection

Support for 8-bit and 16-bit HIC data width modes is controlled via the HICMODECR.DW_MODE register field. In order to perform a 32-bit access, the Host has to initiate four accesses in 8-bit mode, while two accesses are sufficient in the case of 16-bit mode as shown in Table 1. This gives 16-bit data width mode an advantage over the 8-bit mode in terms of raw throughput at the cost of incurring 8 additional I/O pins for data.

Table 1. Host Transaction for Different Data-Width Modes

Intended Write by the Host Data Width Mode Write cycle1 Write cycle2 Write cycle3 Write cycle4
Address = 0x5000
Data = 0x12345678		 16 bits HICDBADDR0 = 0x5000
HIC_A[7:0] (1) = 0x0
HIC_D[15:0] = 0x5678		 HICDBADDR0 = 0x5000
HIC.A[7:0] = 0x1
HIC.D[15:0] = 0x1234		 - -
8 bits HICDBADDR0 = 0x5000
HIC.A[7:0] = 0x0
HIC.D[15:0] = 0x78		 HICDBADDR0 = 0x5000
HIC.A[7:0] = 0x1
HIC.D[15:0] = 0x56		 HICDBADDR0 = 0x5000
HIC.A[7:0] = 0x2
HIC.D[15:0] = 0x34		 HICDBADDR0=0x5000
HIC.A[7:0] = 0x3
HIC.D[15:0] = 0x12
  1. Fields in italics are I/O pins.

The address translation for different data width modes is covered in detail in Section A.