4 PWM Update Latency for Dual Motor

The major challenge in implementing the current loop lies in reducing the latency between feedback sampling and PWM updates. In traditional control schemes, this latency is typically one sampling period, thereby, delaying the control action. In other words, it leads to one sampling period of inaction to any disturbances in the loop. For a fast current loop, this delay must be as small as possible to improve the loop performance over the wide operating speed range of the motor. Typically, a latency of one microsecond or less is considered acceptable in many applications that requires a controller with a fast compute engine, a fast ADC, low latency control peripherals and a superior control algorithm.

On a single F2837x or F28004x, it is possible to run two independent FCLs in less than 2 µs while still supporting the high control bandwidth and double sampling of each axis. In order to maintain the goal of measuring the currents of each motor during voltage transitions, the ADC double sampling is interleaved between each motor so that the sampling and subsequent FOC processing does not need to happen back to back. The motor 1 carrier lags motor 2 by a fixed 90°, then the ADC sampling period is consistent across both motors but interleaved between them as shown in Figure 2. Each ADC sample and conversion is followed by the C2000 CPU performing the FOC algorithm and updating the PWMs. In this way, the sample-to-PWM update remains very consistent for each execution, whether it’s the first or second sample of motor 1 or motor 2.