SNLA246D October   2015  – May 2026 DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1DP83867 Application Overview
  5. 2Troubleshooting the Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Voltage Checks
      2. 2.2.2 Probe the RESET_N Signal
      3. 2.2.3 Probe RBIAS
      4. 2.2.4 Probe the XI Clock
      5. 2.2.5 Probe the Strap Pins During Initialization
      6. 2.2.6 Probe the Serial Management Interface (MDC, MDIO)
        1. 2.2.6.1 Read and Check Register Values
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Check the Link Quality
        1. 2.3.3.1 Improving Short Cable Link Margin
        2. 2.3.3.2 Improving Inter-channel Link Margin
      4. 2.3.4 PMA Compliance
    4. 2.4 MII Health Checks
      1. 2.4.1 MII Check
      2. 2.4.2 GMII Check
      3. 2.4.3 RGMII Check
      4. 2.4.4 SGMII Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets with the MAC
      3. 2.5.3 Transmitting and Receiving Packets with BIST
  6. 3Application Specific Debugs
    1. 3.1 Link up in 100Mbps Full Duplex Force Mode
    2. 3.2 Unstable Link Up Debug in 1Gbps communication
    3. 3.3 DP83867PHY and DP83867PHY Cannot Link Up in 1Gbps
    4. 3.4 EMC Debug
    5. 3.5 Packet Errors in Links with Low IPG
    6. 3.6 10Base-Te TP_IDL Failure
    7. 3.7 Slow RGMII Rise/Fall Times
  7. 4Tools and References
    1. 4.1 Extended Register Access
  8. 5Conclusion
  9. 6References
  10. 7Revision History

2.2.6.1 Read and Check Register Values

Read the registers and verify the default values shown in the data sheet. Note that the initial values of some registers can vary based on strap options. An example of expected register values for PHY operation and link in 100/1000Mbps with auto-negotiation are shown in Table 2-5

The expected register values for PHY operation and link in 1000 Mbps with auto-negotiation enabled are shown in Table 2-4.

Table 2-4 DP83867 Register Value References
Register AddressRegister ValueComments

100Mbps

1000Mbps

0x0000

1140

1140

Auto-negotiation enabled

0x0001

796D

796D

Link

established

0x0004

01E1

01E1

DUT 10/100Mbps advertisement
0x0009

0000

0300

1000Mbps advertisement

0x0011

6C02

BF02

PHY Status

Example: After powering and linking the PHY in 1000Mbps, Reg 0x11 contains the value BF02. This confirms:

  • 1000Mbps Mode

  • Full-Duplex

  • Auto-Negotiation is complete

  • Link Established

Example: After powering and linking the PHY in 10 Mbps, register 0x1 contains the value 0x7969. In this case, bit[2] is low, while the expected value is high. Bit[2] of register 0x1 corresponds to link status, so it is known that the PHY is not linked.

If register access is not readily available, a USB-2-MDIO GUI is available from TI and can be used with an MSP430F5529™ Launchpad, purchasable through the TI eStore. The GUI supports reading and writing registers, running script files, and can be used with the DP83869HM and the other devices in TI's Ethernet portfolio. The USB-2-MDIO User's Guide and GUI are available for download.