SNLA246D October   2015  – May 2026 DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1DP83867 Application Overview
  5. 2Troubleshooting the Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Voltage Checks
      2. 2.2.2 Probe the RESET_N Signal
      3. 2.2.3 Probe RBIAS
      4. 2.2.4 Probe the XI Clock
      5. 2.2.5 Probe the Strap Pins During Initialization
      6. 2.2.6 Probe the Serial Management Interface (MDC, MDIO)
        1. 2.2.6.1 Read and Check Register Values
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Check the Link Quality
        1. 2.3.3.1 Improving Short Cable Link Margin
        2. 2.3.3.2 Improving Inter-channel Link Margin
      4. 2.3.4 PMA Compliance
    4. 2.4 MII Health Checks
      1. 2.4.1 MII Check
      2. 2.4.2 GMII Check
      3. 2.4.3 RGMII Check
      4. 2.4.4 SGMII Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets with the MAC
      3. 2.5.3 Transmitting and Receiving Packets with BIST
  6. 3Application Specific Debugs
    1. 3.1 Link up in 100Mbps Full Duplex Force Mode
    2. 3.2 Unstable Link Up Debug in 1Gbps communication
    3. 3.3 DP83867PHY and DP83867PHY Cannot Link Up in 1Gbps
    4. 3.4 EMC Debug
    5. 3.5 Packet Errors in Links with Low IPG
    6. 3.6 10Base-Te TP_IDL Failure
    7. 3.7 Slow RGMII Rise/Fall Times
  7. 4Tools and References
    1. 4.1 Extended Register Access
  8. 5Conclusion
  9. 6References
  10. 7Revision History

2.2.1 Voltage Checks

DP83867 needs to have sufficient power as well as

  • One 10nF, and one 10uF decoupling per rail

  • One 100nF, and one 1uF decoupling per pin

The DP83867 supports the two configurations for power supplies shown in Figure 2-1 and Figure 2-2.

DP83867 Two Supply ConfigurationFigure 2-1 Two Supply Configuration
DP83867 Three Supply ConfigurationFigure 2-2 Three Supply Configuration

When operating in three-supply configuration, VDDA1P8 must be stable within 25ms of VDDA2P5 ramping up. Make sure to supply VDDIO1P8 after VDDA2V5.

  • When powering down the DP83867, VDDA1P8 needs to be brought down before VDDA2P5.

Power up the device and verify the sequence of these supplies with an oscilloscope. Perform DC measurements of the supplies as close to the pin as possible. Confirm that each measurement is within the limits defined below.

Table 2-1 Recommended Operating Conditions

Min(V)

Typ(V)

Max(V)

VDDIO (1.8V)

1.71

1.8

1.89

VDDIO (2.5V)

2.375

2.5

2.625

VDDIO (3.3V)

3.15

3.3

3.45

VDD1P1 (PAP)

1.045

1.1

1.155

VDD1P0 (RGZ)

0.95

1

1.155

VDDA1P8

1.71

1.8

1.89

VDDA2P5

2.375

2.5

2.625