SNLA246D October   2015  – May 2026 DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1DP83867 Application Overview
  5. 2Troubleshooting the Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Voltage Checks
      2. 2.2.2 Probe the RESET_N Signal
      3. 2.2.3 Probe RBIAS
      4. 2.2.4 Probe the XI Clock
      5. 2.2.5 Probe the Strap Pins During Initialization
      6. 2.2.6 Probe the Serial Management Interface (MDC, MDIO)
        1. 2.2.6.1 Read and Check Register Values
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Check the Link Quality
        1. 2.3.3.1 Improving Short Cable Link Margin
        2. 2.3.3.2 Improving Inter-channel Link Margin
      4. 2.3.4 PMA Compliance
    4. 2.4 MII Health Checks
      1. 2.4.1 MII Check
      2. 2.4.2 GMII Check
      3. 2.4.3 RGMII Check
      4. 2.4.4 SGMII Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets with the MAC
      3. 2.5.3 Transmitting and Receiving Packets with BIST
  6. 3Application Specific Debugs
    1. 3.1 Link up in 100Mbps Full Duplex Force Mode
    2. 3.2 Unstable Link Up Debug in 1Gbps communication
    3. 3.3 DP83867PHY and DP83867PHY Cannot Link Up in 1Gbps
    4. 3.4 EMC Debug
    5. 3.5 Packet Errors in Links with Low IPG
    6. 3.6 10Base-Te TP_IDL Failure
    7. 3.7 Slow RGMII Rise/Fall Times
  7. 4Tools and References
    1. 4.1 Extended Register Access
  8. 5Conclusion
  9. 6References
  10. 7Revision History

2.3.3 Check the Link Quality

After establishing a valid link, confirming the key status register values and visually verifying that the link LED is lit, the next data transfer debug step is to check the MDI Interface. There are several possible sources of link problems:

  1. Link partner transmit problem

  2. Cable length and quality

  3. 25MHz reference clock quality

  4. MDI signal quality

With the PHY powered and connected to a link partner, the following registers can be used to determine the Mean Square Error (MSE). For 100Mbps communication please refer to channel A only. The MSE registers are not valid for 10Mbps communication. With the MSE value, use Table 2-10 to determine the link quality.

Table 2-6 Link Quality MSE Registers for 1000Mbps
ChannelRegister Address
A0x225
B0x265
C0x2A5
D0x2E5

For a given channel, read the register value to determine the MSE (Mean Square Error), convert to decimal, and refer to the following table to determine link quality:

Table 2-7 MSE Link Quality Conversion
Link QualityMSE Range
Excellent

0x020A > MSE

Good

0x33B > MSE > 0x020A

Poor

MSE > 0x33B